xref: /openbmc/qemu/include/hw/core/tcg-cpu-ops.h (revision f6e33708)
1 /*
2  * TCG CPU-specific operations
3  *
4  * Copyright 2021 SUSE LLC
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7  * See the COPYING file in the top-level directory.
8  */
9 
10 #ifndef TCG_CPU_OPS_H
11 #define TCG_CPU_OPS_H
12 
13 #include "hw/core/cpu.h"
14 
15 struct TCGCPUOps {
16     /**
17      * @initialize: Initialize TCG state
18      *
19      * Called when the first CPU is realized.
20      */
21     void (*initialize)(void);
22     /**
23      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
24      *
25      * This is called when we abandon execution of a TB before starting it,
26      * and must set all parts of the CPU state which the previous TB in the
27      * chain may not have updated.
28      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
29      *
30      * If more state needs to be restored, the target must implement a
31      * function to restore all the state, and register it here.
32      */
33     void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
34     /**
35      * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
36      *
37      * This is called when we unwind state in the middle of a TB,
38      * usually before raising an exception.  Set all part of the CPU
39      * state which are tracked insn-by-insn in the target-specific
40      * arguments to start_insn, passed as @data.
41      */
42     void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
43                                  const uint64_t *data);
44 
45     /** @cpu_exec_enter: Callback for cpu_exec preparation */
46     void (*cpu_exec_enter)(CPUState *cpu);
47     /** @cpu_exec_exit: Callback for cpu_exec cleanup */
48     void (*cpu_exec_exit)(CPUState *cpu);
49     /** @debug_excp_handler: Callback for handling debug exceptions */
50     void (*debug_excp_handler)(CPUState *cpu);
51 
52 #ifdef NEED_CPU_H
53 #ifdef CONFIG_USER_ONLY
54     /**
55      * @fake_user_interrupt: Callback for 'fake exception' handling.
56      *
57      * Simulate 'fake exception' which will be handled outside the
58      * cpu execution loop (hack for x86 user mode).
59      */
60     void (*fake_user_interrupt)(CPUState *cpu);
61 
62     /**
63      * record_sigsegv:
64      * @cpu: cpu context
65      * @addr: faulting guest address
66      * @access_type: access was read/write/execute
67      * @maperr: true for invalid page, false for permission fault
68      * @ra: host pc for unwinding
69      *
70      * We are about to raise SIGSEGV with si_code set for @maperr,
71      * and si_addr set for @addr.  Record anything further needed
72      * for the signal ucontext_t.
73      *
74      * If the emulated kernel does not provide anything to the signal
75      * handler with anything besides the user context registers, and
76      * the siginfo_t, then this hook need do nothing and may be omitted.
77      * Otherwise, record the data and return; the caller will raise
78      * the signal, unwind the cpu state, and return to the main loop.
79      *
80      * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
81      * so that a "normal" cpu exception can be raised.  In this case,
82      * the signal must be raised by the architecture cpu_loop.
83      */
84     void (*record_sigsegv)(CPUState *cpu, vaddr addr,
85                            MMUAccessType access_type,
86                            bool maperr, uintptr_t ra);
87     /**
88      * record_sigbus:
89      * @cpu: cpu context
90      * @addr: misaligned guest address
91      * @access_type: access was read/write/execute
92      * @ra: host pc for unwinding
93      *
94      * We are about to raise SIGBUS with si_code BUS_ADRALN,
95      * and si_addr set for @addr.  Record anything further needed
96      * for the signal ucontext_t.
97      *
98      * If the emulated kernel does not provide the signal handler with
99      * anything besides the user context registers, and the siginfo_t,
100      * then this hook need do nothing and may be omitted.
101      * Otherwise, record the data and return; the caller will raise
102      * the signal, unwind the cpu state, and return to the main loop.
103      *
104      * If it is simpler to re-use the sysemu do_unaligned_access code,
105      * @ra is provided so that a "normal" cpu exception can be raised.
106      * In this case, the signal must be raised by the architecture cpu_loop.
107      */
108     void (*record_sigbus)(CPUState *cpu, vaddr addr,
109                           MMUAccessType access_type, uintptr_t ra);
110 #else
111     /** @do_interrupt: Callback for interrupt handling.  */
112     void (*do_interrupt)(CPUState *cpu);
113     /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
114     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
115     /** @cpu_exec_halt: Callback for handling halt in cpu_exec */
116     void (*cpu_exec_halt)(CPUState *cpu);
117     /**
118      * @tlb_fill: Handle a softmmu tlb miss
119      *
120      * If the access is valid, call tlb_set_page and return true;
121      * if the access is invalid and probe is true, return false;
122      * otherwise raise an exception and do not return.
123      */
124     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
125                      MMUAccessType access_type, int mmu_idx,
126                      bool probe, uintptr_t retaddr);
127     /**
128      * @do_transaction_failed: Callback for handling failed memory transactions
129      * (ie bus faults or external aborts; not MMU faults)
130      */
131     void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
132                                   unsigned size, MMUAccessType access_type,
133                                   int mmu_idx, MemTxAttrs attrs,
134                                   MemTxResult response, uintptr_t retaddr);
135     /**
136      * @do_unaligned_access: Callback for unaligned access handling
137      * The callback must exit via raising an exception.
138      */
139     G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
140                                            MMUAccessType access_type,
141                                            int mmu_idx, uintptr_t retaddr);
142 
143     /**
144      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
145      */
146     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
147 
148     /**
149      * @debug_check_watchpoint: return true if the architectural
150      * watchpoint whose address has matched should really fire, used by ARM
151      * and RISC-V
152      */
153     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
154 
155     /**
156      * @debug_check_breakpoint: return true if the architectural
157      * breakpoint whose PC has matched should really fire.
158      */
159     bool (*debug_check_breakpoint)(CPUState *cpu);
160 
161     /**
162      * @io_recompile_replay_branch: Callback for cpu_io_recompile.
163      *
164      * The cpu has been stopped, and cpu_restore_state_from_tb has been
165      * called.  If the faulting instruction is in a delay slot, and the
166      * target architecture requires re-execution of the branch, then
167      * adjust the cpu state as required and return true.
168      */
169     bool (*io_recompile_replay_branch)(CPUState *cpu,
170                                        const TranslationBlock *tb);
171     /**
172      * @need_replay_interrupt: Return %true if @interrupt_request
173      * needs to be recorded for replay purposes.
174      */
175     bool (*need_replay_interrupt)(int interrupt_request);
176 #endif /* !CONFIG_USER_ONLY */
177 #endif /* NEED_CPU_H */
178 
179 };
180 
181 #if defined(CONFIG_USER_ONLY)
182 
183 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
184                                         MemTxAttrs atr, int fl, uintptr_t ra)
185 {
186 }
187 
188 static inline int cpu_watchpoint_address_matches(CPUState *cpu,
189                                                  vaddr addr, vaddr len)
190 {
191     return 0;
192 }
193 
194 #else
195 
196 /**
197  * cpu_check_watchpoint:
198  * @cpu: cpu context
199  * @addr: guest virtual address
200  * @len: access length
201  * @attrs: memory access attributes
202  * @flags: watchpoint access type
203  * @ra: unwind return address
204  *
205  * Check for a watchpoint hit in [addr, addr+len) of the type
206  * specified by @flags.  Exit via exception with a hit.
207  */
208 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
209                           MemTxAttrs attrs, int flags, uintptr_t ra);
210 
211 /**
212  * cpu_watchpoint_address_matches:
213  * @cpu: cpu context
214  * @addr: guest virtual address
215  * @len: access length
216  *
217  * Return the watchpoint flags that apply to [addr, addr+len).
218  * If no watchpoint is registered for the range, the result is 0.
219  */
220 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
221 
222 #endif
223 
224 #endif /* TCG_CPU_OPS_H */
225