1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "hw/core/cpu.h" 14 15 struct TCGCPUOps { 16 /** 17 * @initialize: Initalize TCG state 18 * 19 * Called when the first CPU is realized. 20 */ 21 void (*initialize)(void); 22 /** 23 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 24 * 25 * This is called when we abandon execution of a TB before starting it, 26 * and must set all parts of the CPU state which the previous TB in the 27 * chain may not have updated. 28 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 29 * 30 * If more state needs to be restored, the target must implement a 31 * function to restore all the state, and register it here. 32 */ 33 void (*synchronize_from_tb)(CPUState *cpu, 34 const struct TranslationBlock *tb); 35 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 36 void (*cpu_exec_enter)(CPUState *cpu); 37 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 38 void (*cpu_exec_exit)(CPUState *cpu); 39 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 40 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 41 /** 42 * @do_interrupt: Callback for interrupt handling. 43 * 44 * note that this is in general SOFTMMU only, but it actually isn't 45 * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it 46 * in the SOFTMMU section in general. 47 */ 48 void (*do_interrupt)(CPUState *cpu); 49 /** 50 * @tlb_fill: Handle a softmmu tlb miss or user-only address fault 51 * 52 * For system mode, if the access is valid, call tlb_set_page 53 * and return true; if the access is invalid, and probe is 54 * true, return false; otherwise raise an exception and do 55 * not return. For user-only mode, always raise an exception 56 * and do not return. 57 */ 58 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 59 MMUAccessType access_type, int mmu_idx, 60 bool probe, uintptr_t retaddr); 61 /** @debug_excp_handler: Callback for handling debug exceptions */ 62 void (*debug_excp_handler)(CPUState *cpu); 63 64 #ifdef NEED_CPU_H 65 #ifdef CONFIG_SOFTMMU 66 /** 67 * @do_transaction_failed: Callback for handling failed memory transactions 68 * (ie bus faults or external aborts; not MMU faults) 69 */ 70 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 71 unsigned size, MMUAccessType access_type, 72 int mmu_idx, MemTxAttrs attrs, 73 MemTxResult response, uintptr_t retaddr); 74 /** 75 * @do_unaligned_access: Callback for unaligned access handling 76 */ 77 void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 78 MMUAccessType access_type, 79 int mmu_idx, uintptr_t retaddr); 80 81 /** 82 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 83 */ 84 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 85 86 /** 87 * @debug_check_watchpoint: return true if the architectural 88 * watchpoint whose address has matched should really fire, used by ARM 89 */ 90 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 91 92 #endif /* CONFIG_SOFTMMU */ 93 #endif /* NEED_CPU_H */ 94 95 }; 96 97 #endif /* TCG_CPU_OPS_H */ 98