1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/mmu-access-type.h" 17 #include "exec/vaddr.h" 18 19 struct TCGCPUOps { 20 /** 21 * @initialize: Initialize TCG state 22 * 23 * Called when the first CPU is realized. 24 */ 25 void (*initialize)(void); 26 /** 27 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 28 * 29 * This is called when we abandon execution of a TB before starting it, 30 * and must set all parts of the CPU state which the previous TB in the 31 * chain may not have updated. 32 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 33 * 34 * If more state needs to be restored, the target must implement a 35 * function to restore all the state, and register it here. 36 */ 37 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 38 /** 39 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 40 * 41 * This is called when we unwind state in the middle of a TB, 42 * usually before raising an exception. Set all part of the CPU 43 * state which are tracked insn-by-insn in the target-specific 44 * arguments to start_insn, passed as @data. 45 */ 46 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 47 const uint64_t *data); 48 49 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 50 void (*cpu_exec_enter)(CPUState *cpu); 51 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 52 void (*cpu_exec_exit)(CPUState *cpu); 53 /** @debug_excp_handler: Callback for handling debug exceptions */ 54 void (*debug_excp_handler)(CPUState *cpu); 55 56 #ifdef CONFIG_USER_ONLY 57 /** 58 * @fake_user_interrupt: Callback for 'fake exception' handling. 59 * 60 * Simulate 'fake exception' which will be handled outside the 61 * cpu execution loop (hack for x86 user mode). 62 */ 63 void (*fake_user_interrupt)(CPUState *cpu); 64 65 /** 66 * record_sigsegv: 67 * @cpu: cpu context 68 * @addr: faulting guest address 69 * @access_type: access was read/write/execute 70 * @maperr: true for invalid page, false for permission fault 71 * @ra: host pc for unwinding 72 * 73 * We are about to raise SIGSEGV with si_code set for @maperr, 74 * and si_addr set for @addr. Record anything further needed 75 * for the signal ucontext_t. 76 * 77 * If the emulated kernel does not provide anything to the signal 78 * handler with anything besides the user context registers, and 79 * the siginfo_t, then this hook need do nothing and may be omitted. 80 * Otherwise, record the data and return; the caller will raise 81 * the signal, unwind the cpu state, and return to the main loop. 82 * 83 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 84 * so that a "normal" cpu exception can be raised. In this case, 85 * the signal must be raised by the architecture cpu_loop. 86 */ 87 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 88 MMUAccessType access_type, 89 bool maperr, uintptr_t ra); 90 /** 91 * record_sigbus: 92 * @cpu: cpu context 93 * @addr: misaligned guest address 94 * @access_type: access was read/write/execute 95 * @ra: host pc for unwinding 96 * 97 * We are about to raise SIGBUS with si_code BUS_ADRALN, 98 * and si_addr set for @addr. Record anything further needed 99 * for the signal ucontext_t. 100 * 101 * If the emulated kernel does not provide the signal handler with 102 * anything besides the user context registers, and the siginfo_t, 103 * then this hook need do nothing and may be omitted. 104 * Otherwise, record the data and return; the caller will raise 105 * the signal, unwind the cpu state, and return to the main loop. 106 * 107 * If it is simpler to re-use the sysemu do_unaligned_access code, 108 * @ra is provided so that a "normal" cpu exception can be raised. 109 * In this case, the signal must be raised by the architecture cpu_loop. 110 */ 111 void (*record_sigbus)(CPUState *cpu, vaddr addr, 112 MMUAccessType access_type, uintptr_t ra); 113 #else 114 /** @do_interrupt: Callback for interrupt handling. */ 115 void (*do_interrupt)(CPUState *cpu); 116 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 117 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 118 /** @cpu_exec_halt: Callback for handling halt in cpu_exec */ 119 void (*cpu_exec_halt)(CPUState *cpu); 120 /** 121 * @tlb_fill: Handle a softmmu tlb miss 122 * 123 * If the access is valid, call tlb_set_page and return true; 124 * if the access is invalid and probe is true, return false; 125 * otherwise raise an exception and do not return. 126 */ 127 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 128 MMUAccessType access_type, int mmu_idx, 129 bool probe, uintptr_t retaddr); 130 /** 131 * @do_transaction_failed: Callback for handling failed memory transactions 132 * (ie bus faults or external aborts; not MMU faults) 133 */ 134 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 135 unsigned size, MMUAccessType access_type, 136 int mmu_idx, MemTxAttrs attrs, 137 MemTxResult response, uintptr_t retaddr); 138 /** 139 * @do_unaligned_access: Callback for unaligned access handling 140 * The callback must exit via raising an exception. 141 */ 142 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 143 MMUAccessType access_type, 144 int mmu_idx, uintptr_t retaddr); 145 146 /** 147 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 148 */ 149 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 150 151 /** 152 * @debug_check_watchpoint: return true if the architectural 153 * watchpoint whose address has matched should really fire, used by ARM 154 * and RISC-V 155 */ 156 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 157 158 /** 159 * @debug_check_breakpoint: return true if the architectural 160 * breakpoint whose PC has matched should really fire. 161 */ 162 bool (*debug_check_breakpoint)(CPUState *cpu); 163 164 /** 165 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 166 * 167 * The cpu has been stopped, and cpu_restore_state_from_tb has been 168 * called. If the faulting instruction is in a delay slot, and the 169 * target architecture requires re-execution of the branch, then 170 * adjust the cpu state as required and return true. 171 */ 172 bool (*io_recompile_replay_branch)(CPUState *cpu, 173 const TranslationBlock *tb); 174 /** 175 * @need_replay_interrupt: Return %true if @interrupt_request 176 * needs to be recorded for replay purposes. 177 */ 178 bool (*need_replay_interrupt)(int interrupt_request); 179 #endif /* !CONFIG_USER_ONLY */ 180 }; 181 182 #if defined(CONFIG_USER_ONLY) 183 184 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 185 MemTxAttrs atr, int fl, uintptr_t ra) 186 { 187 } 188 189 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 190 vaddr addr, vaddr len) 191 { 192 return 0; 193 } 194 195 #else 196 197 /** 198 * cpu_check_watchpoint: 199 * @cpu: cpu context 200 * @addr: guest virtual address 201 * @len: access length 202 * @attrs: memory access attributes 203 * @flags: watchpoint access type 204 * @ra: unwind return address 205 * 206 * Check for a watchpoint hit in [addr, addr+len) of the type 207 * specified by @flags. Exit via exception with a hit. 208 */ 209 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 210 MemTxAttrs attrs, int flags, uintptr_t ra); 211 212 /** 213 * cpu_watchpoint_address_matches: 214 * @cpu: cpu context 215 * @addr: guest virtual address 216 * @len: access length 217 * 218 * Return the watchpoint flags that apply to [addr, addr+len). 219 * If no watchpoint is registered for the range, the result is 0. 220 */ 221 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 222 223 #endif 224 225 #endif /* TCG_CPU_OPS_H */ 226