1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "hw/core/cpu.h" 14 15 struct TCGCPUOps { 16 /** 17 * @initialize: Initalize TCG state 18 * 19 * Called when the first CPU is realized. 20 */ 21 void (*initialize)(void); 22 /** 23 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 24 * 25 * This is called when we abandon execution of a TB before starting it, 26 * and must set all parts of the CPU state which the previous TB in the 27 * chain may not have updated. 28 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 29 * 30 * If more state needs to be restored, the target must implement a 31 * function to restore all the state, and register it here. 32 */ 33 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 34 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 35 void (*cpu_exec_enter)(CPUState *cpu); 36 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 37 void (*cpu_exec_exit)(CPUState *cpu); 38 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 39 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 40 /** 41 * @tlb_fill: Handle a softmmu tlb miss or user-only address fault 42 * 43 * For system mode, if the access is valid, call tlb_set_page 44 * and return true; if the access is invalid, and probe is 45 * true, return false; otherwise raise an exception and do 46 * not return. For user-only mode, always raise an exception 47 * and do not return. 48 */ 49 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 50 MMUAccessType access_type, int mmu_idx, 51 bool probe, uintptr_t retaddr); 52 /** @debug_excp_handler: Callback for handling debug exceptions */ 53 void (*debug_excp_handler)(CPUState *cpu); 54 55 #ifdef NEED_CPU_H 56 #if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) 57 /** 58 * @fake_user_interrupt: Callback for 'fake exception' handling. 59 * 60 * Simulate 'fake exception' which will be handled outside the 61 * cpu execution loop (hack for x86 user mode). 62 */ 63 void (*fake_user_interrupt)(CPUState *cpu); 64 #else 65 /** 66 * @do_interrupt: Callback for interrupt handling. 67 */ 68 void (*do_interrupt)(CPUState *cpu); 69 #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ 70 #ifdef CONFIG_SOFTMMU 71 /** 72 * @do_transaction_failed: Callback for handling failed memory transactions 73 * (ie bus faults or external aborts; not MMU faults) 74 */ 75 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 76 unsigned size, MMUAccessType access_type, 77 int mmu_idx, MemTxAttrs attrs, 78 MemTxResult response, uintptr_t retaddr); 79 /** 80 * @do_unaligned_access: Callback for unaligned access handling 81 */ 82 void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 83 MMUAccessType access_type, 84 int mmu_idx, uintptr_t retaddr); 85 86 /** 87 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 88 */ 89 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 90 91 /** 92 * @debug_check_watchpoint: return true if the architectural 93 * watchpoint whose address has matched should really fire, used by ARM 94 */ 95 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 96 97 /** 98 * @debug_check_breakpoint: return true if the architectural 99 * breakpoint whose PC has matched should really fire. 100 */ 101 bool (*debug_check_breakpoint)(CPUState *cpu); 102 103 /** 104 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 105 * 106 * The cpu has been stopped, and cpu_restore_state_from_tb has been 107 * called. If the faulting instruction is in a delay slot, and the 108 * target architecture requires re-execution of the branch, then 109 * adjust the cpu state as required and return true. 110 */ 111 bool (*io_recompile_replay_branch)(CPUState *cpu, 112 const TranslationBlock *tb); 113 #endif /* CONFIG_SOFTMMU */ 114 #endif /* NEED_CPU_H */ 115 116 }; 117 118 #endif /* TCG_CPU_OPS_H */ 119