xref: /openbmc/qemu/include/hw/core/cpu.h (revision 44602af8)
1 /*
2  * QEMU CPU model
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22 
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/cpu-common.h"
26 #include "exec/hwaddr.h"
27 #include "exec/memattrs.h"
28 #include "qapi/qapi-types-run-state.h"
29 #include "qemu/bitmap.h"
30 #include "qemu/rcu_queue.h"
31 #include "qemu/queue.h"
32 #include "qemu/thread.h"
33 #include "qemu/plugin.h"
34 #include "qom/object.h"
35 
36 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
37                                      void *opaque);
38 
39 /**
40  * SECTION:cpu
41  * @section_id: QEMU-cpu
42  * @title: CPU Class
43  * @short_description: Base class for all CPUs
44  */
45 
46 #define TYPE_CPU "cpu"
47 
48 /* Since this macro is used a lot in hot code paths and in conjunction with
49  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
50  * an unchecked cast.
51  */
52 #define CPU(obj) ((CPUState *)(obj))
53 
54 typedef struct CPUClass CPUClass;
55 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
56                        TYPE_CPU)
57 
58 /**
59  * OBJECT_DECLARE_CPU_TYPE:
60  * @CpuInstanceType: instance struct name
61  * @CpuClassType: class struct name
62  * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
63  *
64  * This macro is typically used in "cpu-qom.h" header file, and will:
65  *
66  *   - create the typedefs for the CPU object and class structs
67  *   - register the type for use with g_autoptr
68  *   - provide three standard type cast functions
69  *
70  * The object struct and class struct need to be declared manually.
71  */
72 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
73     typedef struct ArchCPU CpuInstanceType; \
74     OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
75 
76 typedef enum MMUAccessType {
77     MMU_DATA_LOAD  = 0,
78     MMU_DATA_STORE = 1,
79     MMU_INST_FETCH = 2
80 } MMUAccessType;
81 
82 typedef struct CPUWatchpoint CPUWatchpoint;
83 
84 /* see tcg-cpu-ops.h */
85 struct TCGCPUOps;
86 
87 /* see accel-cpu.h */
88 struct AccelCPUClass;
89 
90 /* see sysemu-cpu-ops.h */
91 struct SysemuCPUOps;
92 
93 /**
94  * CPUClass:
95  * @class_by_name: Callback to map -cpu command line model name to an
96  * instantiatable CPU type.
97  * @parse_features: Callback to parse command line arguments.
98  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
99  * @has_work: Callback for checking if there is work to do.
100  * @memory_rw_debug: Callback for GDB memory access.
101  * @dump_state: Callback for dumping state.
102  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
103  * @set_pc: Callback for setting the Program Counter register. This
104  *       should have the semantics used by the target architecture when
105  *       setting the PC from a source such as an ELF file entry point;
106  *       for example on Arm it will also set the Thumb mode bit based
107  *       on the least significant bit of the new PC value.
108  *       If the target behaviour here is anything other than "set
109  *       the PC register to the value passed in" then the target must
110  *       also implement the synchronize_from_tb hook.
111  * @gdb_read_register: Callback for letting GDB read a register.
112  * @gdb_write_register: Callback for letting GDB write a register.
113  * @gdb_adjust_breakpoint: Callback for adjusting the address of a
114  *       breakpoint.  Used by AVR to handle a gdb mis-feature with
115  *       its Harvard architecture split code and data.
116  * @gdb_num_core_regs: Number of core registers accessible to GDB.
117  * @gdb_core_xml_file: File name for core registers GDB XML description.
118  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
119  *           before the insn which triggers a watchpoint rather than after it.
120  * @gdb_arch_name: Optional callback that returns the architecture name known
121  * to GDB. The caller must free the returned string with g_free.
122  * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
123  *   gdb stub. Returns a pointer to the XML contents for the specified XML file
124  *   or NULL if the CPU doesn't have a dynamically generated content for it.
125  * @disas_set_info: Setup architecture specific components of disassembly info
126  * @adjust_watchpoint_address: Perform a target-specific adjustment to an
127  * address before attempting to match it against watchpoints.
128  * @deprecation_note: If this CPUClass is deprecated, this field provides
129  *                    related information.
130  *
131  * Represents a CPU family or model.
132  */
133 struct CPUClass {
134     /*< private >*/
135     DeviceClass parent_class;
136     /*< public >*/
137 
138     ObjectClass *(*class_by_name)(const char *cpu_model);
139     void (*parse_features)(const char *typename, char *str, Error **errp);
140 
141     bool (*has_work)(CPUState *cpu);
142     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
143                            uint8_t *buf, int len, bool is_write);
144     void (*dump_state)(CPUState *cpu, FILE *, int flags);
145     int64_t (*get_arch_id)(CPUState *cpu);
146     void (*set_pc)(CPUState *cpu, vaddr value);
147     int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
148     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
149     vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
150 
151     const char *gdb_core_xml_file;
152     gchar * (*gdb_arch_name)(CPUState *cpu);
153     const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
154 
155     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
156 
157     const char *deprecation_note;
158     struct AccelCPUClass *accel_cpu;
159 
160     /* when system emulation is not available, this pointer is NULL */
161     const struct SysemuCPUOps *sysemu_ops;
162 
163     /* when TCG is not available, this pointer is NULL */
164     const struct TCGCPUOps *tcg_ops;
165 
166     /*
167      * if not NULL, this is called in order for the CPUClass to initialize
168      * class data that depends on the accelerator, see accel/accel-common.c.
169      */
170     void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
171 
172     /*
173      * Keep non-pointer data at the end to minimize holes.
174      */
175     int reset_dump_flags;
176     int gdb_num_core_regs;
177     bool gdb_stop_before_watchpoint;
178 };
179 
180 /*
181  * Low 16 bits: number of cycles left, used only in icount mode.
182  * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
183  * for this CPU and return to its top level loop (even in non-icount mode).
184  * This allows a single read-compare-cbranch-write sequence to test
185  * for both decrementer underflow and exceptions.
186  */
187 typedef union IcountDecr {
188     uint32_t u32;
189     struct {
190 #if HOST_BIG_ENDIAN
191         uint16_t high;
192         uint16_t low;
193 #else
194         uint16_t low;
195         uint16_t high;
196 #endif
197     } u16;
198 } IcountDecr;
199 
200 typedef struct CPUBreakpoint {
201     vaddr pc;
202     int flags; /* BP_* */
203     QTAILQ_ENTRY(CPUBreakpoint) entry;
204 } CPUBreakpoint;
205 
206 struct CPUWatchpoint {
207     vaddr vaddr;
208     vaddr len;
209     vaddr hitaddr;
210     MemTxAttrs hitattrs;
211     int flags; /* BP_* */
212     QTAILQ_ENTRY(CPUWatchpoint) entry;
213 };
214 
215 #ifdef CONFIG_PLUGIN
216 /*
217  * For plugins we sometime need to save the resolved iotlb data before
218  * the memory regions get moved around  by io_writex.
219  */
220 typedef struct SavedIOTLB {
221     hwaddr addr;
222     MemoryRegionSection *section;
223     hwaddr mr_offset;
224 } SavedIOTLB;
225 #endif
226 
227 struct KVMState;
228 struct kvm_run;
229 
230 struct hax_vcpu_state;
231 struct hvf_vcpu_state;
232 
233 #define TB_JMP_CACHE_BITS 12
234 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
235 
236 /* work queue */
237 
238 /* The union type allows passing of 64 bit target pointers on 32 bit
239  * hosts in a single parameter
240  */
241 typedef union {
242     int           host_int;
243     unsigned long host_ulong;
244     void         *host_ptr;
245     vaddr         target_ptr;
246 } run_on_cpu_data;
247 
248 #define RUN_ON_CPU_HOST_PTR(p)    ((run_on_cpu_data){.host_ptr = (p)})
249 #define RUN_ON_CPU_HOST_INT(i)    ((run_on_cpu_data){.host_int = (i)})
250 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
251 #define RUN_ON_CPU_TARGET_PTR(v)  ((run_on_cpu_data){.target_ptr = (v)})
252 #define RUN_ON_CPU_NULL           RUN_ON_CPU_HOST_PTR(NULL)
253 
254 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
255 
256 struct qemu_work_item;
257 
258 #define CPU_UNSET_NUMA_NODE_ID -1
259 #define CPU_TRACE_DSTATE_MAX_EVENTS 32
260 
261 /**
262  * CPUState:
263  * @cpu_index: CPU index (informative).
264  * @cluster_index: Identifies which cluster this CPU is in.
265  *   For boards which don't define clusters or for "loose" CPUs not assigned
266  *   to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
267  *   be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
268  *   QOM parent.
269  * @tcg_cflags: Pre-computed cflags for this cpu.
270  * @nr_cores: Number of cores within this CPU package.
271  * @nr_threads: Number of threads within this CPU.
272  * @running: #true if CPU is currently running (lockless).
273  * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
274  * valid under cpu_list_lock.
275  * @created: Indicates whether the CPU thread has been successfully created.
276  * @interrupt_request: Indicates a pending interrupt request.
277  * @halted: Nonzero if the CPU is in suspended state.
278  * @stop: Indicates a pending stop request.
279  * @stopped: Indicates the CPU has been artificially stopped.
280  * @unplug: Indicates a pending CPU unplug request.
281  * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
282  * @singlestep_enabled: Flags for single-stepping.
283  * @icount_extra: Instructions until next timer event.
284  * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
285  * requires that IO only be performed on the last instruction of a TB
286  * so that interrupts take effect immediately.
287  * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
288  *            AddressSpaces this CPU has)
289  * @num_ases: number of CPUAddressSpaces in @cpu_ases
290  * @as: Pointer to the first AddressSpace, for the convenience of targets which
291  *      only have a single AddressSpace
292  * @env_ptr: Pointer to subclass-specific CPUArchState field.
293  * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
294  * @gdb_regs: Additional GDB registers.
295  * @gdb_num_regs: Number of total registers accessible to GDB.
296  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
297  * @next_cpu: Next CPU sharing TB cache.
298  * @opaque: User data.
299  * @mem_io_pc: Host Program Counter at which the memory was accessed.
300  * @kvm_fd: vCPU file descriptor for KVM.
301  * @work_mutex: Lock to prevent multiple access to @work_list.
302  * @work_list: List of pending asynchronous work.
303  * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
304  *                        to @trace_dstate).
305  * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
306  * @plugin_mask: Plugin event bitmap. Modified only via async work.
307  * @ignore_memory_transaction_failures: Cached copy of the MachineState
308  *    flag of the same name: allows the board to suppress calling of the
309  *    CPU do_transaction_failed hook function.
310  * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
311  *    ring is enabled.
312  * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
313  *    dirty ring structure.
314  *
315  * State of one CPU core or thread.
316  */
317 struct CPUState {
318     /*< private >*/
319     DeviceState parent_obj;
320     /*< public >*/
321 
322     int nr_cores;
323     int nr_threads;
324 
325     struct QemuThread *thread;
326 #ifdef _WIN32
327     HANDLE hThread;
328 #endif
329     int thread_id;
330     bool running, has_waiter;
331     struct QemuCond *halt_cond;
332     bool thread_kicked;
333     bool created;
334     bool stop;
335     bool stopped;
336 
337     /* Should CPU start in powered-off state? */
338     bool start_powered_off;
339 
340     bool unplug;
341     bool crash_occurred;
342     bool exit_request;
343     bool in_exclusive_context;
344     uint32_t cflags_next_tb;
345     /* updates protected by BQL */
346     uint32_t interrupt_request;
347     int singlestep_enabled;
348     int64_t icount_budget;
349     int64_t icount_extra;
350     uint64_t random_seed;
351     sigjmp_buf jmp_env;
352 
353     QemuMutex work_mutex;
354     QSIMPLEQ_HEAD(, qemu_work_item) work_list;
355 
356     CPUAddressSpace *cpu_ases;
357     int num_ases;
358     AddressSpace *as;
359     MemoryRegion *memory;
360 
361     CPUArchState *env_ptr;
362     IcountDecr *icount_decr_ptr;
363 
364     /* Accessed in parallel; all accesses must be atomic */
365     TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
366 
367     struct GDBRegisterState *gdb_regs;
368     int gdb_num_regs;
369     int gdb_num_g_regs;
370     QTAILQ_ENTRY(CPUState) node;
371 
372     /* ice debug support */
373     QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
374 
375     QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
376     CPUWatchpoint *watchpoint_hit;
377 
378     void *opaque;
379 
380     /* In order to avoid passing too many arguments to the MMIO helpers,
381      * we store some rarely used information in the CPU context.
382      */
383     uintptr_t mem_io_pc;
384 
385     /* Only used in KVM */
386     int kvm_fd;
387     struct KVMState *kvm_state;
388     struct kvm_run *kvm_run;
389     struct kvm_dirty_gfn *kvm_dirty_gfns;
390     uint32_t kvm_fetch_index;
391     uint64_t dirty_pages;
392 
393     /* Used for events with 'vcpu' and *without* the 'disabled' properties */
394     DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
395     DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS);
396 
397     DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX);
398 
399 #ifdef CONFIG_PLUGIN
400     GArray *plugin_mem_cbs;
401     /* saved iotlb data from io_writex */
402     SavedIOTLB saved_iotlb;
403 #endif
404 
405     /* TODO Move common fields from CPUArchState here. */
406     int cpu_index;
407     int cluster_index;
408     uint32_t tcg_cflags;
409     uint32_t halted;
410     uint32_t can_do_io;
411     int32_t exception_index;
412 
413     /* shared by kvm, hax and hvf */
414     bool vcpu_dirty;
415 
416     /* Used to keep track of an outstanding cpu throttle thread for migration
417      * autoconverge
418      */
419     bool throttle_thread_scheduled;
420 
421     /*
422      * Sleep throttle_us_per_full microseconds once dirty ring is full
423      * if dirty page rate limit is enabled.
424      */
425     int64_t throttle_us_per_full;
426 
427     bool ignore_memory_transaction_failures;
428 
429     /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
430     bool prctl_unalign_sigbus;
431 
432     struct hax_vcpu_state *hax_vcpu;
433 
434     struct hvf_vcpu_state *hvf;
435 
436     /* track IOMMUs whose translations we've cached in the TCG TLB */
437     GArray *iommu_notifiers;
438 };
439 
440 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
441 extern CPUTailQ cpus;
442 
443 #define first_cpu        QTAILQ_FIRST_RCU(&cpus)
444 #define CPU_NEXT(cpu)    QTAILQ_NEXT_RCU(cpu, node)
445 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
446 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
447     QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
448 
449 extern __thread CPUState *current_cpu;
450 
451 static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
452 {
453     unsigned int i;
454 
455     for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
456         qatomic_set(&cpu->tb_jmp_cache[i], NULL);
457     }
458 }
459 
460 /**
461  * qemu_tcg_mttcg_enabled:
462  * Check whether we are running MultiThread TCG or not.
463  *
464  * Returns: %true if we are in MTTCG mode %false otherwise.
465  */
466 extern bool mttcg_enabled;
467 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
468 
469 /**
470  * cpu_paging_enabled:
471  * @cpu: The CPU whose state is to be inspected.
472  *
473  * Returns: %true if paging is enabled, %false otherwise.
474  */
475 bool cpu_paging_enabled(const CPUState *cpu);
476 
477 /**
478  * cpu_get_memory_mapping:
479  * @cpu: The CPU whose memory mappings are to be obtained.
480  * @list: Where to write the memory mappings to.
481  * @errp: Pointer for reporting an #Error.
482  */
483 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
484                             Error **errp);
485 
486 #if !defined(CONFIG_USER_ONLY)
487 
488 /**
489  * cpu_write_elf64_note:
490  * @f: pointer to a function that writes memory to a file
491  * @cpu: The CPU whose memory is to be dumped
492  * @cpuid: ID number of the CPU
493  * @opaque: pointer to the CPUState struct
494  */
495 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
496                          int cpuid, void *opaque);
497 
498 /**
499  * cpu_write_elf64_qemunote:
500  * @f: pointer to a function that writes memory to a file
501  * @cpu: The CPU whose memory is to be dumped
502  * @cpuid: ID number of the CPU
503  * @opaque: pointer to the CPUState struct
504  */
505 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
506                              void *opaque);
507 
508 /**
509  * cpu_write_elf32_note:
510  * @f: pointer to a function that writes memory to a file
511  * @cpu: The CPU whose memory is to be dumped
512  * @cpuid: ID number of the CPU
513  * @opaque: pointer to the CPUState struct
514  */
515 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
516                          int cpuid, void *opaque);
517 
518 /**
519  * cpu_write_elf32_qemunote:
520  * @f: pointer to a function that writes memory to a file
521  * @cpu: The CPU whose memory is to be dumped
522  * @cpuid: ID number of the CPU
523  * @opaque: pointer to the CPUState struct
524  */
525 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
526                              void *opaque);
527 
528 /**
529  * cpu_get_crash_info:
530  * @cpu: The CPU to get crash information for
531  *
532  * Gets the previously saved crash information.
533  * Caller is responsible for freeing the data.
534  */
535 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
536 
537 #endif /* !CONFIG_USER_ONLY */
538 
539 /**
540  * CPUDumpFlags:
541  * @CPU_DUMP_CODE:
542  * @CPU_DUMP_FPU: dump FPU register state, not just integer
543  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
544  */
545 enum CPUDumpFlags {
546     CPU_DUMP_CODE = 0x00010000,
547     CPU_DUMP_FPU  = 0x00020000,
548     CPU_DUMP_CCOP = 0x00040000,
549 };
550 
551 /**
552  * cpu_dump_state:
553  * @cpu: The CPU whose state is to be dumped.
554  * @f: If non-null, dump to this stream, else to current print sink.
555  *
556  * Dumps CPU state.
557  */
558 void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
559 
560 #ifndef CONFIG_USER_ONLY
561 /**
562  * cpu_get_phys_page_attrs_debug:
563  * @cpu: The CPU to obtain the physical page address for.
564  * @addr: The virtual address.
565  * @attrs: Updated on return with the memory transaction attributes to use
566  *         for this access.
567  *
568  * Obtains the physical page corresponding to a virtual one, together
569  * with the corresponding memory transaction attributes to use for the access.
570  * Use it only for debugging because no protection checks are done.
571  *
572  * Returns: Corresponding physical page address or -1 if no page found.
573  */
574 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
575                                      MemTxAttrs *attrs);
576 
577 /**
578  * cpu_get_phys_page_debug:
579  * @cpu: The CPU to obtain the physical page address for.
580  * @addr: The virtual address.
581  *
582  * Obtains the physical page corresponding to a virtual one.
583  * Use it only for debugging because no protection checks are done.
584  *
585  * Returns: Corresponding physical page address or -1 if no page found.
586  */
587 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
588 
589 /** cpu_asidx_from_attrs:
590  * @cpu: CPU
591  * @attrs: memory transaction attributes
592  *
593  * Returns the address space index specifying the CPU AddressSpace
594  * to use for a memory access with the given transaction attributes.
595  */
596 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
597 
598 /**
599  * cpu_virtio_is_big_endian:
600  * @cpu: CPU
601 
602  * Returns %true if a CPU which supports runtime configurable endianness
603  * is currently big-endian.
604  */
605 bool cpu_virtio_is_big_endian(CPUState *cpu);
606 
607 #endif /* CONFIG_USER_ONLY */
608 
609 /**
610  * cpu_list_add:
611  * @cpu: The CPU to be added to the list of CPUs.
612  */
613 void cpu_list_add(CPUState *cpu);
614 
615 /**
616  * cpu_list_remove:
617  * @cpu: The CPU to be removed from the list of CPUs.
618  */
619 void cpu_list_remove(CPUState *cpu);
620 
621 /**
622  * cpu_reset:
623  * @cpu: The CPU whose state is to be reset.
624  */
625 void cpu_reset(CPUState *cpu);
626 
627 /**
628  * cpu_class_by_name:
629  * @typename: The CPU base type.
630  * @cpu_model: The model string without any parameters.
631  *
632  * Looks up a CPU #ObjectClass matching name @cpu_model.
633  *
634  * Returns: A #CPUClass or %NULL if not matching class is found.
635  */
636 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
637 
638 /**
639  * cpu_create:
640  * @typename: The CPU type.
641  *
642  * Instantiates a CPU and realizes the CPU.
643  *
644  * Returns: A #CPUState or %NULL if an error occurred.
645  */
646 CPUState *cpu_create(const char *typename);
647 
648 /**
649  * parse_cpu_option:
650  * @cpu_option: The -cpu option including optional parameters.
651  *
652  * processes optional parameters and registers them as global properties
653  *
654  * Returns: type of CPU to create or prints error and terminates process
655  *          if an error occurred.
656  */
657 const char *parse_cpu_option(const char *cpu_option);
658 
659 /**
660  * cpu_has_work:
661  * @cpu: The vCPU to check.
662  *
663  * Checks whether the CPU has work to do.
664  *
665  * Returns: %true if the CPU has work, %false otherwise.
666  */
667 static inline bool cpu_has_work(CPUState *cpu)
668 {
669     CPUClass *cc = CPU_GET_CLASS(cpu);
670 
671     g_assert(cc->has_work);
672     return cc->has_work(cpu);
673 }
674 
675 /**
676  * qemu_cpu_is_self:
677  * @cpu: The vCPU to check against.
678  *
679  * Checks whether the caller is executing on the vCPU thread.
680  *
681  * Returns: %true if called from @cpu's thread, %false otherwise.
682  */
683 bool qemu_cpu_is_self(CPUState *cpu);
684 
685 /**
686  * qemu_cpu_kick:
687  * @cpu: The vCPU to kick.
688  *
689  * Kicks @cpu's thread.
690  */
691 void qemu_cpu_kick(CPUState *cpu);
692 
693 /**
694  * cpu_is_stopped:
695  * @cpu: The CPU to check.
696  *
697  * Checks whether the CPU is stopped.
698  *
699  * Returns: %true if run state is not running or if artificially stopped;
700  * %false otherwise.
701  */
702 bool cpu_is_stopped(CPUState *cpu);
703 
704 /**
705  * do_run_on_cpu:
706  * @cpu: The vCPU to run on.
707  * @func: The function to be executed.
708  * @data: Data to pass to the function.
709  * @mutex: Mutex to release while waiting for @func to run.
710  *
711  * Used internally in the implementation of run_on_cpu.
712  */
713 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
714                    QemuMutex *mutex);
715 
716 /**
717  * run_on_cpu:
718  * @cpu: The vCPU to run on.
719  * @func: The function to be executed.
720  * @data: Data to pass to the function.
721  *
722  * Schedules the function @func for execution on the vCPU @cpu.
723  */
724 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
725 
726 /**
727  * async_run_on_cpu:
728  * @cpu: The vCPU to run on.
729  * @func: The function to be executed.
730  * @data: Data to pass to the function.
731  *
732  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
733  */
734 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
735 
736 /**
737  * async_safe_run_on_cpu:
738  * @cpu: The vCPU to run on.
739  * @func: The function to be executed.
740  * @data: Data to pass to the function.
741  *
742  * Schedules the function @func for execution on the vCPU @cpu asynchronously,
743  * while all other vCPUs are sleeping.
744  *
745  * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
746  * BQL.
747  */
748 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
749 
750 /**
751  * cpu_in_exclusive_context()
752  * @cpu: The vCPU to check
753  *
754  * Returns true if @cpu is an exclusive context, for example running
755  * something which has previously been queued via async_safe_run_on_cpu().
756  */
757 static inline bool cpu_in_exclusive_context(const CPUState *cpu)
758 {
759     return cpu->in_exclusive_context;
760 }
761 
762 /**
763  * qemu_get_cpu:
764  * @index: The CPUState@cpu_index value of the CPU to obtain.
765  *
766  * Gets a CPU matching @index.
767  *
768  * Returns: The CPU or %NULL if there is no matching CPU.
769  */
770 CPUState *qemu_get_cpu(int index);
771 
772 /**
773  * cpu_exists:
774  * @id: Guest-exposed CPU ID to lookup.
775  *
776  * Search for CPU with specified ID.
777  *
778  * Returns: %true - CPU is found, %false - CPU isn't found.
779  */
780 bool cpu_exists(int64_t id);
781 
782 /**
783  * cpu_by_arch_id:
784  * @id: Guest-exposed CPU ID of the CPU to obtain.
785  *
786  * Get a CPU with matching @id.
787  *
788  * Returns: The CPU or %NULL if there is no matching CPU.
789  */
790 CPUState *cpu_by_arch_id(int64_t id);
791 
792 /**
793  * cpu_interrupt:
794  * @cpu: The CPU to set an interrupt on.
795  * @mask: The interrupts to set.
796  *
797  * Invokes the interrupt handler.
798  */
799 
800 void cpu_interrupt(CPUState *cpu, int mask);
801 
802 /**
803  * cpu_set_pc:
804  * @cpu: The CPU to set the program counter for.
805  * @addr: Program counter value.
806  *
807  * Sets the program counter for a CPU.
808  */
809 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
810 {
811     CPUClass *cc = CPU_GET_CLASS(cpu);
812 
813     cc->set_pc(cpu, addr);
814 }
815 
816 /**
817  * cpu_reset_interrupt:
818  * @cpu: The CPU to clear the interrupt on.
819  * @mask: The interrupt mask to clear.
820  *
821  * Resets interrupts on the vCPU @cpu.
822  */
823 void cpu_reset_interrupt(CPUState *cpu, int mask);
824 
825 /**
826  * cpu_exit:
827  * @cpu: The CPU to exit.
828  *
829  * Requests the CPU @cpu to exit execution.
830  */
831 void cpu_exit(CPUState *cpu);
832 
833 /**
834  * cpu_resume:
835  * @cpu: The CPU to resume.
836  *
837  * Resumes CPU, i.e. puts CPU into runnable state.
838  */
839 void cpu_resume(CPUState *cpu);
840 
841 /**
842  * cpu_remove_sync:
843  * @cpu: The CPU to remove.
844  *
845  * Requests the CPU to be removed and waits till it is removed.
846  */
847 void cpu_remove_sync(CPUState *cpu);
848 
849 /**
850  * process_queued_cpu_work() - process all items on CPU work queue
851  * @cpu: The CPU which work queue to process.
852  */
853 void process_queued_cpu_work(CPUState *cpu);
854 
855 /**
856  * cpu_exec_start:
857  * @cpu: The CPU for the current thread.
858  *
859  * Record that a CPU has started execution and can be interrupted with
860  * cpu_exit.
861  */
862 void cpu_exec_start(CPUState *cpu);
863 
864 /**
865  * cpu_exec_end:
866  * @cpu: The CPU for the current thread.
867  *
868  * Record that a CPU has stopped execution and exclusive sections
869  * can be executed without interrupting it.
870  */
871 void cpu_exec_end(CPUState *cpu);
872 
873 /**
874  * start_exclusive:
875  *
876  * Wait for a concurrent exclusive section to end, and then start
877  * a section of work that is run while other CPUs are not running
878  * between cpu_exec_start and cpu_exec_end.  CPUs that are running
879  * cpu_exec are exited immediately.  CPUs that call cpu_exec_start
880  * during the exclusive section go to sleep until this CPU calls
881  * end_exclusive.
882  */
883 void start_exclusive(void);
884 
885 /**
886  * end_exclusive:
887  *
888  * Concludes an exclusive execution section started by start_exclusive.
889  */
890 void end_exclusive(void);
891 
892 /**
893  * qemu_init_vcpu:
894  * @cpu: The vCPU to initialize.
895  *
896  * Initializes a vCPU.
897  */
898 void qemu_init_vcpu(CPUState *cpu);
899 
900 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
901 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
902 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
903 
904 /**
905  * cpu_single_step:
906  * @cpu: CPU to the flags for.
907  * @enabled: Flags to enable.
908  *
909  * Enables or disables single-stepping for @cpu.
910  */
911 void cpu_single_step(CPUState *cpu, int enabled);
912 
913 /* Breakpoint/watchpoint flags */
914 #define BP_MEM_READ           0x01
915 #define BP_MEM_WRITE          0x02
916 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
917 #define BP_STOP_BEFORE_ACCESS 0x04
918 /* 0x08 currently unused */
919 #define BP_GDB                0x10
920 #define BP_CPU                0x20
921 #define BP_ANY                (BP_GDB | BP_CPU)
922 #define BP_WATCHPOINT_HIT_READ 0x40
923 #define BP_WATCHPOINT_HIT_WRITE 0x80
924 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
925 
926 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
927                           CPUBreakpoint **breakpoint);
928 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
929 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
930 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
931 
932 /* Return true if PC matches an installed breakpoint.  */
933 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
934 {
935     CPUBreakpoint *bp;
936 
937     if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
938         QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
939             if (bp->pc == pc && (bp->flags & mask)) {
940                 return true;
941             }
942         }
943     }
944     return false;
945 }
946 
947 #ifdef CONFIG_USER_ONLY
948 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
949                                         int flags, CPUWatchpoint **watchpoint)
950 {
951     return -ENOSYS;
952 }
953 
954 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
955                                         vaddr len, int flags)
956 {
957     return -ENOSYS;
958 }
959 
960 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
961                                                 CPUWatchpoint *wp)
962 {
963 }
964 
965 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
966 {
967 }
968 
969 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
970                                         MemTxAttrs atr, int fl, uintptr_t ra)
971 {
972 }
973 
974 static inline int cpu_watchpoint_address_matches(CPUState *cpu,
975                                                  vaddr addr, vaddr len)
976 {
977     return 0;
978 }
979 #else
980 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
981                           int flags, CPUWatchpoint **watchpoint);
982 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
983                           vaddr len, int flags);
984 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
985 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
986 
987 /**
988  * cpu_check_watchpoint:
989  * @cpu: cpu context
990  * @addr: guest virtual address
991  * @len: access length
992  * @attrs: memory access attributes
993  * @flags: watchpoint access type
994  * @ra: unwind return address
995  *
996  * Check for a watchpoint hit in [addr, addr+len) of the type
997  * specified by @flags.  Exit via exception with a hit.
998  */
999 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
1000                           MemTxAttrs attrs, int flags, uintptr_t ra);
1001 
1002 /**
1003  * cpu_watchpoint_address_matches:
1004  * @cpu: cpu context
1005  * @addr: guest virtual address
1006  * @len: access length
1007  *
1008  * Return the watchpoint flags that apply to [addr, addr+len).
1009  * If no watchpoint is registered for the range, the result is 0.
1010  */
1011 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
1012 #endif
1013 
1014 /**
1015  * cpu_get_address_space:
1016  * @cpu: CPU to get address space from
1017  * @asidx: index identifying which address space to get
1018  *
1019  * Return the requested address space of this CPU. @asidx
1020  * specifies which address space to read.
1021  */
1022 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1023 
1024 G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
1025     G_GNUC_PRINTF(2, 3);
1026 
1027 /* $(top_srcdir)/cpu.c */
1028 void cpu_class_init_props(DeviceClass *dc);
1029 void cpu_exec_initfn(CPUState *cpu);
1030 void cpu_exec_realizefn(CPUState *cpu, Error **errp);
1031 void cpu_exec_unrealizefn(CPUState *cpu);
1032 
1033 /**
1034  * target_words_bigendian:
1035  * Returns true if the (default) endianness of the target is big endian,
1036  * false otherwise. Note that in target-specific code, you can use
1037  * TARGET_BIG_ENDIAN directly instead. On the other hand, common
1038  * code should normally never need to know about the endianness of the
1039  * target, so please do *not* use this function unless you know very well
1040  * what you are doing!
1041  */
1042 bool target_words_bigendian(void);
1043 
1044 void page_size_init(void);
1045 
1046 #ifdef NEED_CPU_H
1047 
1048 #ifdef CONFIG_SOFTMMU
1049 
1050 extern const VMStateDescription vmstate_cpu_common;
1051 
1052 #define VMSTATE_CPU() {                                                     \
1053     .name = "parent_obj",                                                   \
1054     .size = sizeof(CPUState),                                               \
1055     .vmsd = &vmstate_cpu_common,                                            \
1056     .flags = VMS_STRUCT,                                                    \
1057     .offset = 0,                                                            \
1058 }
1059 #endif /* CONFIG_SOFTMMU */
1060 
1061 #endif /* NEED_CPU_H */
1062 
1063 #define UNASSIGNED_CPU_INDEX -1
1064 #define UNASSIGNED_CLUSTER_INDEX -1
1065 
1066 #endif
1067