1 /* 2 * QEMU CPU model 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 #ifndef QEMU_CPU_H 21 #define QEMU_CPU_H 22 23 #include "hw/qdev-core.h" 24 #include "disas/dis-asm.h" 25 #include "exec/hwaddr.h" 26 #include "exec/memattrs.h" 27 #include "qapi/qapi-types-run-state.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/rcu_queue.h" 30 #include "qemu/queue.h" 31 #include "qemu/thread.h" 32 #include "qemu/plugin.h" 33 #include "qom/object.h" 34 35 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, 36 void *opaque); 37 38 /** 39 * vaddr: 40 * Type wide enough to contain any #target_ulong virtual address. 41 */ 42 typedef uint64_t vaddr; 43 #define VADDR_PRId PRId64 44 #define VADDR_PRIu PRIu64 45 #define VADDR_PRIo PRIo64 46 #define VADDR_PRIx PRIx64 47 #define VADDR_PRIX PRIX64 48 #define VADDR_MAX UINT64_MAX 49 50 /** 51 * SECTION:cpu 52 * @section_id: QEMU-cpu 53 * @title: CPU Class 54 * @short_description: Base class for all CPUs 55 */ 56 57 #define TYPE_CPU "cpu" 58 59 /* Since this macro is used a lot in hot code paths and in conjunction with 60 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using 61 * an unchecked cast. 62 */ 63 #define CPU(obj) ((CPUState *)(obj)) 64 65 typedef struct CPUClass CPUClass; 66 DECLARE_CLASS_CHECKERS(CPUClass, CPU, 67 TYPE_CPU) 68 69 typedef enum MMUAccessType { 70 MMU_DATA_LOAD = 0, 71 MMU_DATA_STORE = 1, 72 MMU_INST_FETCH = 2 73 } MMUAccessType; 74 75 typedef struct CPUWatchpoint CPUWatchpoint; 76 77 struct TranslationBlock; 78 79 /** 80 * CPUClass: 81 * @class_by_name: Callback to map -cpu command line model name to an 82 * instantiatable CPU type. 83 * @parse_features: Callback to parse command line arguments. 84 * @reset_dump_flags: #CPUDumpFlags to use for reset logging. 85 * @has_work: Callback for checking if there is work to do. 86 * @do_interrupt: Callback for interrupt handling. 87 * @do_unaligned_access: Callback for unaligned access handling, if 88 * the target defines #TARGET_ALIGNED_ONLY. 89 * @do_transaction_failed: Callback for handling failed memory transactions 90 * (ie bus faults or external aborts; not MMU faults) 91 * @virtio_is_big_endian: Callback to return %true if a CPU which supports 92 * runtime configurable endianness is currently big-endian. Non-configurable 93 * CPUs can use the default implementation of this method. This method should 94 * not be used by any callers other than the pre-1.0 virtio devices. 95 * @memory_rw_debug: Callback for GDB memory access. 96 * @dump_state: Callback for dumping state. 97 * @dump_statistics: Callback for dumping statistics. 98 * @get_arch_id: Callback for getting architecture-dependent CPU ID. 99 * @get_paging_enabled: Callback for inquiring whether paging is enabled. 100 * @get_memory_mapping: Callback for obtaining the memory mappings. 101 * @set_pc: Callback for setting the Program Counter register. This 102 * should have the semantics used by the target architecture when 103 * setting the PC from a source such as an ELF file entry point; 104 * for example on Arm it will also set the Thumb mode bit based 105 * on the least significant bit of the new PC value. 106 * If the target behaviour here is anything other than "set 107 * the PC register to the value passed in" then the target must 108 * also implement the synchronize_from_tb hook. 109 * @synchronize_from_tb: Callback for synchronizing state from a TCG 110 * #TranslationBlock. This is called when we abandon execution 111 * of a TB before starting it, and must set all parts of the CPU 112 * state which the previous TB in the chain may not have updated. 113 * This always includes at least the program counter; some targets 114 * will need to do more. If this hook is not implemented then the 115 * default is to call @set_pc(tb->pc). 116 * @tlb_fill: Callback for handling a softmmu tlb miss or user-only 117 * address fault. For system mode, if the access is valid, call 118 * tlb_set_page and return true; if the access is invalid, and 119 * probe is true, return false; otherwise raise an exception and 120 * do not return. For user-only mode, always raise an exception 121 * and do not return. 122 * @get_phys_page_debug: Callback for obtaining a physical address. 123 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the 124 * associated memory transaction attributes to use for the access. 125 * CPUs which use memory transaction attributes should implement this 126 * instead of get_phys_page_debug. 127 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for 128 * a memory access with the specified memory transaction attributes. 129 * @gdb_read_register: Callback for letting GDB read a register. 130 * @gdb_write_register: Callback for letting GDB write a register. 131 * @debug_check_watchpoint: Callback: return true if the architectural 132 * watchpoint whose address has matched should really fire. 133 * @debug_excp_handler: Callback for handling debug exceptions. 134 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a 135 * 64-bit VM coredump. 136 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 137 * note to a 32-bit VM coredump. 138 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a 139 * 32-bit VM coredump. 140 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 141 * note to a 32-bit VM coredump. 142 * @vmsd: State description for migration. 143 * @gdb_num_core_regs: Number of core registers accessible to GDB. 144 * @gdb_core_xml_file: File name for core registers GDB XML description. 145 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop 146 * before the insn which triggers a watchpoint rather than after it. 147 * @gdb_arch_name: Optional callback that returns the architecture name known 148 * to GDB. The caller must free the returned string with g_free. 149 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the 150 * gdb stub. Returns a pointer to the XML contents for the specified XML file 151 * or NULL if the CPU doesn't have a dynamically generated content for it. 152 * @cpu_exec_enter: Callback for cpu_exec preparation. 153 * @cpu_exec_exit: Callback for cpu_exec cleanup. 154 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. 155 * @disas_set_info: Setup architecture specific components of disassembly info 156 * @adjust_watchpoint_address: Perform a target-specific adjustment to an 157 * address before attempting to match it against watchpoints. 158 * 159 * Represents a CPU family or model. 160 */ 161 struct CPUClass { 162 /*< private >*/ 163 DeviceClass parent_class; 164 /*< public >*/ 165 166 ObjectClass *(*class_by_name)(const char *cpu_model); 167 void (*parse_features)(const char *typename, char *str, Error **errp); 168 169 int reset_dump_flags; 170 bool (*has_work)(CPUState *cpu); 171 void (*do_interrupt)(CPUState *cpu); 172 void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 173 MMUAccessType access_type, 174 int mmu_idx, uintptr_t retaddr); 175 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 176 unsigned size, MMUAccessType access_type, 177 int mmu_idx, MemTxAttrs attrs, 178 MemTxResult response, uintptr_t retaddr); 179 bool (*virtio_is_big_endian)(CPUState *cpu); 180 int (*memory_rw_debug)(CPUState *cpu, vaddr addr, 181 uint8_t *buf, int len, bool is_write); 182 void (*dump_state)(CPUState *cpu, FILE *, int flags); 183 GuestPanicInformation* (*get_crash_info)(CPUState *cpu); 184 void (*dump_statistics)(CPUState *cpu, int flags); 185 int64_t (*get_arch_id)(CPUState *cpu); 186 bool (*get_paging_enabled)(const CPUState *cpu); 187 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, 188 Error **errp); 189 void (*set_pc)(CPUState *cpu, vaddr value); 190 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); 191 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 192 MMUAccessType access_type, int mmu_idx, 193 bool probe, uintptr_t retaddr); 194 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); 195 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, 196 MemTxAttrs *attrs); 197 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); 198 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); 199 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); 200 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 201 void (*debug_excp_handler)(CPUState *cpu); 202 203 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, 204 int cpuid, void *opaque); 205 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 206 void *opaque); 207 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, 208 int cpuid, void *opaque); 209 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 210 void *opaque); 211 212 const VMStateDescription *vmsd; 213 const char *gdb_core_xml_file; 214 gchar * (*gdb_arch_name)(CPUState *cpu); 215 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); 216 void (*cpu_exec_enter)(CPUState *cpu); 217 void (*cpu_exec_exit)(CPUState *cpu); 218 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 219 220 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); 221 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 222 void (*tcg_initialize)(void); 223 224 /* Keep non-pointer data at the end to minimize holes. */ 225 int gdb_num_core_regs; 226 bool gdb_stop_before_watchpoint; 227 }; 228 229 /* 230 * Low 16 bits: number of cycles left, used only in icount mode. 231 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs 232 * for this CPU and return to its top level loop (even in non-icount mode). 233 * This allows a single read-compare-cbranch-write sequence to test 234 * for both decrementer underflow and exceptions. 235 */ 236 typedef union IcountDecr { 237 uint32_t u32; 238 struct { 239 #ifdef HOST_WORDS_BIGENDIAN 240 uint16_t high; 241 uint16_t low; 242 #else 243 uint16_t low; 244 uint16_t high; 245 #endif 246 } u16; 247 } IcountDecr; 248 249 typedef struct CPUBreakpoint { 250 vaddr pc; 251 int flags; /* BP_* */ 252 QTAILQ_ENTRY(CPUBreakpoint) entry; 253 } CPUBreakpoint; 254 255 struct CPUWatchpoint { 256 vaddr vaddr; 257 vaddr len; 258 vaddr hitaddr; 259 MemTxAttrs hitattrs; 260 int flags; /* BP_* */ 261 QTAILQ_ENTRY(CPUWatchpoint) entry; 262 }; 263 264 #ifdef CONFIG_PLUGIN 265 /* 266 * For plugins we sometime need to save the resolved iotlb data before 267 * the memory regions get moved around by io_writex. 268 */ 269 typedef struct SavedIOTLB { 270 hwaddr addr; 271 MemoryRegionSection *section; 272 hwaddr mr_offset; 273 } SavedIOTLB; 274 #endif 275 276 struct KVMState; 277 struct kvm_run; 278 279 struct hax_vcpu_state; 280 281 #define TB_JMP_CACHE_BITS 12 282 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 283 284 /* work queue */ 285 286 /* The union type allows passing of 64 bit target pointers on 32 bit 287 * hosts in a single parameter 288 */ 289 typedef union { 290 int host_int; 291 unsigned long host_ulong; 292 void *host_ptr; 293 vaddr target_ptr; 294 } run_on_cpu_data; 295 296 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) 297 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) 298 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) 299 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) 300 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) 301 302 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); 303 304 struct qemu_work_item; 305 306 #define CPU_UNSET_NUMA_NODE_ID -1 307 #define CPU_TRACE_DSTATE_MAX_EVENTS 32 308 309 /** 310 * CPUState: 311 * @cpu_index: CPU index (informative). 312 * @cluster_index: Identifies which cluster this CPU is in. 313 * For boards which don't define clusters or for "loose" CPUs not assigned 314 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will 315 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER 316 * QOM parent. 317 * @nr_cores: Number of cores within this CPU package. 318 * @nr_threads: Number of threads within this CPU. 319 * @running: #true if CPU is currently running (lockless). 320 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; 321 * valid under cpu_list_lock. 322 * @created: Indicates whether the CPU thread has been successfully created. 323 * @interrupt_request: Indicates a pending interrupt request. 324 * @halted: Nonzero if the CPU is in suspended state. 325 * @stop: Indicates a pending stop request. 326 * @stopped: Indicates the CPU has been artificially stopped. 327 * @unplug: Indicates a pending CPU unplug request. 328 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU 329 * @singlestep_enabled: Flags for single-stepping. 330 * @icount_extra: Instructions until next timer event. 331 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution 332 * requires that IO only be performed on the last instruction of a TB 333 * so that interrupts take effect immediately. 334 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the 335 * AddressSpaces this CPU has) 336 * @num_ases: number of CPUAddressSpaces in @cpu_ases 337 * @as: Pointer to the first AddressSpace, for the convenience of targets which 338 * only have a single AddressSpace 339 * @env_ptr: Pointer to subclass-specific CPUArchState field. 340 * @icount_decr_ptr: Pointer to IcountDecr field within subclass. 341 * @gdb_regs: Additional GDB registers. 342 * @gdb_num_regs: Number of total registers accessible to GDB. 343 * @gdb_num_g_regs: Number of registers in GDB 'g' packets. 344 * @next_cpu: Next CPU sharing TB cache. 345 * @opaque: User data. 346 * @mem_io_pc: Host Program Counter at which the memory was accessed. 347 * @kvm_fd: vCPU file descriptor for KVM. 348 * @work_mutex: Lock to prevent multiple access to @work_list. 349 * @work_list: List of pending asynchronous work. 350 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes 351 * to @trace_dstate). 352 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). 353 * @plugin_mask: Plugin event bitmap. Modified only via async work. 354 * @ignore_memory_transaction_failures: Cached copy of the MachineState 355 * flag of the same name: allows the board to suppress calling of the 356 * CPU do_transaction_failed hook function. 357 * 358 * State of one CPU core or thread. 359 */ 360 struct CPUState { 361 /*< private >*/ 362 DeviceState parent_obj; 363 /*< public >*/ 364 365 int nr_cores; 366 int nr_threads; 367 368 struct QemuThread *thread; 369 #ifdef _WIN32 370 HANDLE hThread; 371 #endif 372 int thread_id; 373 bool running, has_waiter; 374 struct QemuCond *halt_cond; 375 bool thread_kicked; 376 bool created; 377 bool stop; 378 bool stopped; 379 380 /* Should CPU start in powered-off state? */ 381 bool start_powered_off; 382 383 bool unplug; 384 bool crash_occurred; 385 bool exit_request; 386 bool in_exclusive_context; 387 uint32_t cflags_next_tb; 388 /* updates protected by BQL */ 389 uint32_t interrupt_request; 390 int singlestep_enabled; 391 int64_t icount_budget; 392 int64_t icount_extra; 393 uint64_t random_seed; 394 sigjmp_buf jmp_env; 395 396 QemuMutex work_mutex; 397 QSIMPLEQ_HEAD(, qemu_work_item) work_list; 398 399 CPUAddressSpace *cpu_ases; 400 int num_ases; 401 AddressSpace *as; 402 MemoryRegion *memory; 403 404 void *env_ptr; /* CPUArchState */ 405 IcountDecr *icount_decr_ptr; 406 407 /* Accessed in parallel; all accesses must be atomic */ 408 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; 409 410 struct GDBRegisterState *gdb_regs; 411 int gdb_num_regs; 412 int gdb_num_g_regs; 413 QTAILQ_ENTRY(CPUState) node; 414 415 /* ice debug support */ 416 QTAILQ_HEAD(, CPUBreakpoint) breakpoints; 417 418 QTAILQ_HEAD(, CPUWatchpoint) watchpoints; 419 CPUWatchpoint *watchpoint_hit; 420 421 void *opaque; 422 423 /* In order to avoid passing too many arguments to the MMIO helpers, 424 * we store some rarely used information in the CPU context. 425 */ 426 uintptr_t mem_io_pc; 427 428 int kvm_fd; 429 struct KVMState *kvm_state; 430 struct kvm_run *kvm_run; 431 432 /* Used for events with 'vcpu' and *without* the 'disabled' properties */ 433 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); 434 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); 435 436 DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); 437 438 #ifdef CONFIG_PLUGIN 439 GArray *plugin_mem_cbs; 440 /* saved iotlb data from io_writex */ 441 SavedIOTLB saved_iotlb; 442 #endif 443 444 /* TODO Move common fields from CPUArchState here. */ 445 int cpu_index; 446 int cluster_index; 447 uint32_t halted; 448 uint32_t can_do_io; 449 int32_t exception_index; 450 451 /* shared by kvm, hax and hvf */ 452 bool vcpu_dirty; 453 454 /* Used to keep track of an outstanding cpu throttle thread for migration 455 * autoconverge 456 */ 457 bool throttle_thread_scheduled; 458 459 bool ignore_memory_transaction_failures; 460 461 struct hax_vcpu_state *hax_vcpu; 462 463 int hvf_fd; 464 465 /* track IOMMUs whose translations we've cached in the TCG TLB */ 466 GArray *iommu_notifiers; 467 }; 468 469 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; 470 extern CPUTailQ cpus; 471 472 #define first_cpu QTAILQ_FIRST_RCU(&cpus) 473 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) 474 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) 475 #define CPU_FOREACH_SAFE(cpu, next_cpu) \ 476 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) 477 478 extern __thread CPUState *current_cpu; 479 480 static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) 481 { 482 unsigned int i; 483 484 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { 485 qatomic_set(&cpu->tb_jmp_cache[i], NULL); 486 } 487 } 488 489 /** 490 * qemu_tcg_mttcg_enabled: 491 * Check whether we are running MultiThread TCG or not. 492 * 493 * Returns: %true if we are in MTTCG mode %false otherwise. 494 */ 495 extern bool mttcg_enabled; 496 #define qemu_tcg_mttcg_enabled() (mttcg_enabled) 497 498 /** 499 * cpu_paging_enabled: 500 * @cpu: The CPU whose state is to be inspected. 501 * 502 * Returns: %true if paging is enabled, %false otherwise. 503 */ 504 bool cpu_paging_enabled(const CPUState *cpu); 505 506 /** 507 * cpu_get_memory_mapping: 508 * @cpu: The CPU whose memory mappings are to be obtained. 509 * @list: Where to write the memory mappings to. 510 * @errp: Pointer for reporting an #Error. 511 */ 512 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 513 Error **errp); 514 515 #if !defined(CONFIG_USER_ONLY) 516 517 /** 518 * cpu_write_elf64_note: 519 * @f: pointer to a function that writes memory to a file 520 * @cpu: The CPU whose memory is to be dumped 521 * @cpuid: ID number of the CPU 522 * @opaque: pointer to the CPUState struct 523 */ 524 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 525 int cpuid, void *opaque); 526 527 /** 528 * cpu_write_elf64_qemunote: 529 * @f: pointer to a function that writes memory to a file 530 * @cpu: The CPU whose memory is to be dumped 531 * @cpuid: ID number of the CPU 532 * @opaque: pointer to the CPUState struct 533 */ 534 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 535 void *opaque); 536 537 /** 538 * cpu_write_elf32_note: 539 * @f: pointer to a function that writes memory to a file 540 * @cpu: The CPU whose memory is to be dumped 541 * @cpuid: ID number of the CPU 542 * @opaque: pointer to the CPUState struct 543 */ 544 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 545 int cpuid, void *opaque); 546 547 /** 548 * cpu_write_elf32_qemunote: 549 * @f: pointer to a function that writes memory to a file 550 * @cpu: The CPU whose memory is to be dumped 551 * @cpuid: ID number of the CPU 552 * @opaque: pointer to the CPUState struct 553 */ 554 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 555 void *opaque); 556 557 /** 558 * cpu_get_crash_info: 559 * @cpu: The CPU to get crash information for 560 * 561 * Gets the previously saved crash information. 562 * Caller is responsible for freeing the data. 563 */ 564 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); 565 566 #endif /* !CONFIG_USER_ONLY */ 567 568 /** 569 * CPUDumpFlags: 570 * @CPU_DUMP_CODE: 571 * @CPU_DUMP_FPU: dump FPU register state, not just integer 572 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state 573 */ 574 enum CPUDumpFlags { 575 CPU_DUMP_CODE = 0x00010000, 576 CPU_DUMP_FPU = 0x00020000, 577 CPU_DUMP_CCOP = 0x00040000, 578 }; 579 580 /** 581 * cpu_dump_state: 582 * @cpu: The CPU whose state is to be dumped. 583 * @f: If non-null, dump to this stream, else to current print sink. 584 * 585 * Dumps CPU state. 586 */ 587 void cpu_dump_state(CPUState *cpu, FILE *f, int flags); 588 589 /** 590 * cpu_dump_statistics: 591 * @cpu: The CPU whose state is to be dumped. 592 * @flags: Flags what to dump. 593 * 594 * Dump CPU statistics to the current monitor if we have one, else to 595 * stdout. 596 */ 597 void cpu_dump_statistics(CPUState *cpu, int flags); 598 599 #ifndef CONFIG_USER_ONLY 600 /** 601 * cpu_get_phys_page_attrs_debug: 602 * @cpu: The CPU to obtain the physical page address for. 603 * @addr: The virtual address. 604 * @attrs: Updated on return with the memory transaction attributes to use 605 * for this access. 606 * 607 * Obtains the physical page corresponding to a virtual one, together 608 * with the corresponding memory transaction attributes to use for the access. 609 * Use it only for debugging because no protection checks are done. 610 * 611 * Returns: Corresponding physical page address or -1 if no page found. 612 */ 613 static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 614 MemTxAttrs *attrs) 615 { 616 CPUClass *cc = CPU_GET_CLASS(cpu); 617 618 if (cc->get_phys_page_attrs_debug) { 619 return cc->get_phys_page_attrs_debug(cpu, addr, attrs); 620 } 621 /* Fallback for CPUs which don't implement the _attrs_ hook */ 622 *attrs = MEMTXATTRS_UNSPECIFIED; 623 return cc->get_phys_page_debug(cpu, addr); 624 } 625 626 /** 627 * cpu_get_phys_page_debug: 628 * @cpu: The CPU to obtain the physical page address for. 629 * @addr: The virtual address. 630 * 631 * Obtains the physical page corresponding to a virtual one. 632 * Use it only for debugging because no protection checks are done. 633 * 634 * Returns: Corresponding physical page address or -1 if no page found. 635 */ 636 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) 637 { 638 MemTxAttrs attrs = {}; 639 640 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); 641 } 642 643 /** cpu_asidx_from_attrs: 644 * @cpu: CPU 645 * @attrs: memory transaction attributes 646 * 647 * Returns the address space index specifying the CPU AddressSpace 648 * to use for a memory access with the given transaction attributes. 649 */ 650 static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) 651 { 652 CPUClass *cc = CPU_GET_CLASS(cpu); 653 int ret = 0; 654 655 if (cc->asidx_from_attrs) { 656 ret = cc->asidx_from_attrs(cpu, attrs); 657 assert(ret < cpu->num_ases && ret >= 0); 658 } 659 return ret; 660 } 661 662 #endif /* CONFIG_USER_ONLY */ 663 664 /** 665 * cpu_list_add: 666 * @cpu: The CPU to be added to the list of CPUs. 667 */ 668 void cpu_list_add(CPUState *cpu); 669 670 /** 671 * cpu_list_remove: 672 * @cpu: The CPU to be removed from the list of CPUs. 673 */ 674 void cpu_list_remove(CPUState *cpu); 675 676 /** 677 * cpu_reset: 678 * @cpu: The CPU whose state is to be reset. 679 */ 680 void cpu_reset(CPUState *cpu); 681 682 /** 683 * cpu_class_by_name: 684 * @typename: The CPU base type. 685 * @cpu_model: The model string without any parameters. 686 * 687 * Looks up a CPU #ObjectClass matching name @cpu_model. 688 * 689 * Returns: A #CPUClass or %NULL if not matching class is found. 690 */ 691 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); 692 693 /** 694 * cpu_create: 695 * @typename: The CPU type. 696 * 697 * Instantiates a CPU and realizes the CPU. 698 * 699 * Returns: A #CPUState or %NULL if an error occurred. 700 */ 701 CPUState *cpu_create(const char *typename); 702 703 /** 704 * parse_cpu_option: 705 * @cpu_option: The -cpu option including optional parameters. 706 * 707 * processes optional parameters and registers them as global properties 708 * 709 * Returns: type of CPU to create or prints error and terminates process 710 * if an error occurred. 711 */ 712 const char *parse_cpu_option(const char *cpu_option); 713 714 /** 715 * cpu_has_work: 716 * @cpu: The vCPU to check. 717 * 718 * Checks whether the CPU has work to do. 719 * 720 * Returns: %true if the CPU has work, %false otherwise. 721 */ 722 static inline bool cpu_has_work(CPUState *cpu) 723 { 724 CPUClass *cc = CPU_GET_CLASS(cpu); 725 726 g_assert(cc->has_work); 727 return cc->has_work(cpu); 728 } 729 730 /** 731 * qemu_cpu_is_self: 732 * @cpu: The vCPU to check against. 733 * 734 * Checks whether the caller is executing on the vCPU thread. 735 * 736 * Returns: %true if called from @cpu's thread, %false otherwise. 737 */ 738 bool qemu_cpu_is_self(CPUState *cpu); 739 740 /** 741 * qemu_cpu_kick: 742 * @cpu: The vCPU to kick. 743 * 744 * Kicks @cpu's thread. 745 */ 746 void qemu_cpu_kick(CPUState *cpu); 747 748 /** 749 * cpu_is_stopped: 750 * @cpu: The CPU to check. 751 * 752 * Checks whether the CPU is stopped. 753 * 754 * Returns: %true if run state is not running or if artificially stopped; 755 * %false otherwise. 756 */ 757 bool cpu_is_stopped(CPUState *cpu); 758 759 /** 760 * do_run_on_cpu: 761 * @cpu: The vCPU to run on. 762 * @func: The function to be executed. 763 * @data: Data to pass to the function. 764 * @mutex: Mutex to release while waiting for @func to run. 765 * 766 * Used internally in the implementation of run_on_cpu. 767 */ 768 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, 769 QemuMutex *mutex); 770 771 /** 772 * run_on_cpu: 773 * @cpu: The vCPU to run on. 774 * @func: The function to be executed. 775 * @data: Data to pass to the function. 776 * 777 * Schedules the function @func for execution on the vCPU @cpu. 778 */ 779 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 780 781 /** 782 * async_run_on_cpu: 783 * @cpu: The vCPU to run on. 784 * @func: The function to be executed. 785 * @data: Data to pass to the function. 786 * 787 * Schedules the function @func for execution on the vCPU @cpu asynchronously. 788 */ 789 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 790 791 /** 792 * async_safe_run_on_cpu: 793 * @cpu: The vCPU to run on. 794 * @func: The function to be executed. 795 * @data: Data to pass to the function. 796 * 797 * Schedules the function @func for execution on the vCPU @cpu asynchronously, 798 * while all other vCPUs are sleeping. 799 * 800 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the 801 * BQL. 802 */ 803 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 804 805 /** 806 * cpu_in_exclusive_context() 807 * @cpu: The vCPU to check 808 * 809 * Returns true if @cpu is an exclusive context, for example running 810 * something which has previously been queued via async_safe_run_on_cpu(). 811 */ 812 static inline bool cpu_in_exclusive_context(const CPUState *cpu) 813 { 814 return cpu->in_exclusive_context; 815 } 816 817 /** 818 * qemu_get_cpu: 819 * @index: The CPUState@cpu_index value of the CPU to obtain. 820 * 821 * Gets a CPU matching @index. 822 * 823 * Returns: The CPU or %NULL if there is no matching CPU. 824 */ 825 CPUState *qemu_get_cpu(int index); 826 827 /** 828 * cpu_exists: 829 * @id: Guest-exposed CPU ID to lookup. 830 * 831 * Search for CPU with specified ID. 832 * 833 * Returns: %true - CPU is found, %false - CPU isn't found. 834 */ 835 bool cpu_exists(int64_t id); 836 837 /** 838 * cpu_by_arch_id: 839 * @id: Guest-exposed CPU ID of the CPU to obtain. 840 * 841 * Get a CPU with matching @id. 842 * 843 * Returns: The CPU or %NULL if there is no matching CPU. 844 */ 845 CPUState *cpu_by_arch_id(int64_t id); 846 847 /** 848 * cpu_interrupt: 849 * @cpu: The CPU to set an interrupt on. 850 * @mask: The interrupts to set. 851 * 852 * Invokes the interrupt handler. 853 */ 854 855 void cpu_interrupt(CPUState *cpu, int mask); 856 857 #ifdef NEED_CPU_H 858 859 #ifdef CONFIG_SOFTMMU 860 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, 861 MMUAccessType access_type, 862 int mmu_idx, uintptr_t retaddr) 863 { 864 CPUClass *cc = CPU_GET_CLASS(cpu); 865 866 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); 867 } 868 869 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, 870 vaddr addr, unsigned size, 871 MMUAccessType access_type, 872 int mmu_idx, MemTxAttrs attrs, 873 MemTxResult response, 874 uintptr_t retaddr) 875 { 876 CPUClass *cc = CPU_GET_CLASS(cpu); 877 878 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { 879 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, 880 mmu_idx, attrs, response, retaddr); 881 } 882 } 883 #endif 884 885 #endif /* NEED_CPU_H */ 886 887 /** 888 * cpu_set_pc: 889 * @cpu: The CPU to set the program counter for. 890 * @addr: Program counter value. 891 * 892 * Sets the program counter for a CPU. 893 */ 894 static inline void cpu_set_pc(CPUState *cpu, vaddr addr) 895 { 896 CPUClass *cc = CPU_GET_CLASS(cpu); 897 898 cc->set_pc(cpu, addr); 899 } 900 901 /** 902 * cpu_reset_interrupt: 903 * @cpu: The CPU to clear the interrupt on. 904 * @mask: The interrupt mask to clear. 905 * 906 * Resets interrupts on the vCPU @cpu. 907 */ 908 void cpu_reset_interrupt(CPUState *cpu, int mask); 909 910 /** 911 * cpu_exit: 912 * @cpu: The CPU to exit. 913 * 914 * Requests the CPU @cpu to exit execution. 915 */ 916 void cpu_exit(CPUState *cpu); 917 918 /** 919 * cpu_resume: 920 * @cpu: The CPU to resume. 921 * 922 * Resumes CPU, i.e. puts CPU into runnable state. 923 */ 924 void cpu_resume(CPUState *cpu); 925 926 /** 927 * cpu_remove: 928 * @cpu: The CPU to remove. 929 * 930 * Requests the CPU to be removed. 931 */ 932 void cpu_remove(CPUState *cpu); 933 934 /** 935 * cpu_remove_sync: 936 * @cpu: The CPU to remove. 937 * 938 * Requests the CPU to be removed and waits till it is removed. 939 */ 940 void cpu_remove_sync(CPUState *cpu); 941 942 /** 943 * process_queued_cpu_work() - process all items on CPU work queue 944 * @cpu: The CPU which work queue to process. 945 */ 946 void process_queued_cpu_work(CPUState *cpu); 947 948 /** 949 * cpu_exec_start: 950 * @cpu: The CPU for the current thread. 951 * 952 * Record that a CPU has started execution and can be interrupted with 953 * cpu_exit. 954 */ 955 void cpu_exec_start(CPUState *cpu); 956 957 /** 958 * cpu_exec_end: 959 * @cpu: The CPU for the current thread. 960 * 961 * Record that a CPU has stopped execution and exclusive sections 962 * can be executed without interrupting it. 963 */ 964 void cpu_exec_end(CPUState *cpu); 965 966 /** 967 * start_exclusive: 968 * 969 * Wait for a concurrent exclusive section to end, and then start 970 * a section of work that is run while other CPUs are not running 971 * between cpu_exec_start and cpu_exec_end. CPUs that are running 972 * cpu_exec are exited immediately. CPUs that call cpu_exec_start 973 * during the exclusive section go to sleep until this CPU calls 974 * end_exclusive. 975 */ 976 void start_exclusive(void); 977 978 /** 979 * end_exclusive: 980 * 981 * Concludes an exclusive execution section started by start_exclusive. 982 */ 983 void end_exclusive(void); 984 985 /** 986 * qemu_init_vcpu: 987 * @cpu: The vCPU to initialize. 988 * 989 * Initializes a vCPU. 990 */ 991 void qemu_init_vcpu(CPUState *cpu); 992 993 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ 994 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ 995 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ 996 997 /** 998 * cpu_single_step: 999 * @cpu: CPU to the flags for. 1000 * @enabled: Flags to enable. 1001 * 1002 * Enables or disables single-stepping for @cpu. 1003 */ 1004 void cpu_single_step(CPUState *cpu, int enabled); 1005 1006 /* Breakpoint/watchpoint flags */ 1007 #define BP_MEM_READ 0x01 1008 #define BP_MEM_WRITE 0x02 1009 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 1010 #define BP_STOP_BEFORE_ACCESS 0x04 1011 /* 0x08 currently unused */ 1012 #define BP_GDB 0x10 1013 #define BP_CPU 0x20 1014 #define BP_ANY (BP_GDB | BP_CPU) 1015 #define BP_WATCHPOINT_HIT_READ 0x40 1016 #define BP_WATCHPOINT_HIT_WRITE 0x80 1017 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) 1018 1019 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, 1020 CPUBreakpoint **breakpoint); 1021 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); 1022 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); 1023 void cpu_breakpoint_remove_all(CPUState *cpu, int mask); 1024 1025 /* Return true if PC matches an installed breakpoint. */ 1026 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) 1027 { 1028 CPUBreakpoint *bp; 1029 1030 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { 1031 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 1032 if (bp->pc == pc && (bp->flags & mask)) { 1033 return true; 1034 } 1035 } 1036 } 1037 return false; 1038 } 1039 1040 #ifdef CONFIG_USER_ONLY 1041 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1042 int flags, CPUWatchpoint **watchpoint) 1043 { 1044 return -ENOSYS; 1045 } 1046 1047 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1048 vaddr len, int flags) 1049 { 1050 return -ENOSYS; 1051 } 1052 1053 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, 1054 CPUWatchpoint *wp) 1055 { 1056 } 1057 1058 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) 1059 { 1060 } 1061 1062 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 1063 MemTxAttrs atr, int fl, uintptr_t ra) 1064 { 1065 } 1066 1067 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 1068 vaddr addr, vaddr len) 1069 { 1070 return 0; 1071 } 1072 #else 1073 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1074 int flags, CPUWatchpoint **watchpoint); 1075 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1076 vaddr len, int flags); 1077 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); 1078 void cpu_watchpoint_remove_all(CPUState *cpu, int mask); 1079 1080 /** 1081 * cpu_check_watchpoint: 1082 * @cpu: cpu context 1083 * @addr: guest virtual address 1084 * @len: access length 1085 * @attrs: memory access attributes 1086 * @flags: watchpoint access type 1087 * @ra: unwind return address 1088 * 1089 * Check for a watchpoint hit in [addr, addr+len) of the type 1090 * specified by @flags. Exit via exception with a hit. 1091 */ 1092 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 1093 MemTxAttrs attrs, int flags, uintptr_t ra); 1094 1095 /** 1096 * cpu_watchpoint_address_matches: 1097 * @cpu: cpu context 1098 * @addr: guest virtual address 1099 * @len: access length 1100 * 1101 * Return the watchpoint flags that apply to [addr, addr+len). 1102 * If no watchpoint is registered for the range, the result is 0. 1103 */ 1104 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 1105 #endif 1106 1107 /** 1108 * cpu_get_address_space: 1109 * @cpu: CPU to get address space from 1110 * @asidx: index identifying which address space to get 1111 * 1112 * Return the requested address space of this CPU. @asidx 1113 * specifies which address space to read. 1114 */ 1115 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); 1116 1117 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) 1118 GCC_FMT_ATTR(2, 3); 1119 extern Property cpu_common_props[]; 1120 void cpu_exec_initfn(CPUState *cpu); 1121 void cpu_exec_realizefn(CPUState *cpu, Error **errp); 1122 void cpu_exec_unrealizefn(CPUState *cpu); 1123 1124 /** 1125 * target_words_bigendian: 1126 * Returns true if the (default) endianness of the target is big endian, 1127 * false otherwise. Note that in target-specific code, you can use 1128 * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common 1129 * code should normally never need to know about the endianness of the 1130 * target, so please do *not* use this function unless you know very well 1131 * what you are doing! 1132 */ 1133 bool target_words_bigendian(void); 1134 1135 #ifdef NEED_CPU_H 1136 1137 #ifdef CONFIG_SOFTMMU 1138 extern const VMStateDescription vmstate_cpu_common; 1139 #else 1140 #define vmstate_cpu_common vmstate_dummy 1141 #endif 1142 1143 #define VMSTATE_CPU() { \ 1144 .name = "parent_obj", \ 1145 .size = sizeof(CPUState), \ 1146 .vmsd = &vmstate_cpu_common, \ 1147 .flags = VMS_STRUCT, \ 1148 .offset = 0, \ 1149 } 1150 1151 #endif /* NEED_CPU_H */ 1152 1153 #define UNASSIGNED_CPU_INDEX -1 1154 #define UNASSIGNED_CLUSTER_INDEX -1 1155 1156 #endif 1157