1 /* 2 * SiFive UART interface 3 * 4 * Copyright (c) 2016 Stefan O'Rear 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_SIFIVE_UART_H 21 #define HW_SIFIVE_UART_H 22 23 #include "chardev/char-fe.h" 24 #include "hw/sysbus.h" 25 #include "qom/object.h" 26 27 enum { 28 SIFIVE_UART_TXFIFO = 0, 29 SIFIVE_UART_RXFIFO = 4, 30 SIFIVE_UART_TXCTRL = 8, 31 SIFIVE_UART_TXMARK = 10, 32 SIFIVE_UART_RXCTRL = 12, 33 SIFIVE_UART_RXMARK = 14, 34 SIFIVE_UART_IE = 16, 35 SIFIVE_UART_IP = 20, 36 SIFIVE_UART_DIV = 24, 37 SIFIVE_UART_MAX = 32 38 }; 39 40 enum { 41 SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */ 42 SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */ 43 }; 44 45 enum { 46 SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */ 47 SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ 48 }; 49 50 #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) 51 #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) 52 53 #define TYPE_SIFIVE_UART "riscv.sifive.uart" 54 55 typedef struct SiFiveUARTState SiFiveUARTState; 56 DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART, 57 TYPE_SIFIVE_UART) 58 59 struct SiFiveUARTState { 60 /*< private >*/ 61 SysBusDevice parent_obj; 62 63 /*< public >*/ 64 qemu_irq irq; 65 MemoryRegion mmio; 66 CharBackend chr; 67 uint8_t rx_fifo[8]; 68 unsigned int rx_fifo_len; 69 uint32_t ie; 70 uint32_t ip; 71 uint32_t txctrl; 72 uint32_t rxctrl; 73 uint32_t div; 74 }; 75 76 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, 77 Chardev *chr, qemu_irq irq); 78 79 #endif 80