1 /* 2 * QEMU 16550A UART emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2008 Citrix Systems, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #ifndef HW_SERIAL_H 27 #define HW_SERIAL_H 28 29 #include "hw/hw.h" 30 #include "sysemu/sysemu.h" 31 #include "chardev/char-fe.h" 32 #include "exec/memory.h" 33 #include "qemu/fifo8.h" 34 #include "chardev/char.h" 35 36 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ 37 38 typedef struct SerialState { 39 uint16_t divider; 40 uint8_t rbr; /* receive register */ 41 uint8_t thr; /* transmit holding register */ 42 uint8_t tsr; /* transmit shift register */ 43 uint8_t ier; 44 uint8_t iir; /* read only */ 45 uint8_t lcr; 46 uint8_t mcr; 47 uint8_t lsr; /* read only */ 48 uint8_t msr; /* read only */ 49 uint8_t scr; 50 uint8_t fcr; 51 uint8_t fcr_vmstate; /* we can't write directly this value 52 it has side effects */ 53 /* NOTE: this hidden state is necessary for tx irq generation as 54 it can be reset while reading iir */ 55 int thr_ipending; 56 qemu_irq irq; 57 CharBackend chr; 58 int last_break_enable; 59 int it_shift; 60 int baudbase; 61 uint32_t tsr_retry; 62 guint watch_tag; 63 uint32_t wakeup; 64 65 /* Time when the last byte was successfully sent out of the tsr */ 66 uint64_t last_xmit_ts; 67 Fifo8 recv_fifo; 68 Fifo8 xmit_fifo; 69 /* Interrupt trigger level for recv_fifo */ 70 uint8_t recv_fifo_itl; 71 72 QEMUTimer *fifo_timeout_timer; 73 int timeout_ipending; /* timeout interrupt pending state */ 74 75 uint64_t char_transmit_time; /* time to transmit a char in ticks */ 76 int poll_msl; 77 78 QEMUTimer *modem_status_poll; 79 MemoryRegion io; 80 } SerialState; 81 82 extern const VMStateDescription vmstate_serial; 83 extern const MemoryRegionOps serial_io_ops; 84 85 void serial_realize_core(SerialState *s, Error **errp); 86 void serial_exit_core(SerialState *s); 87 void serial_set_frequency(SerialState *s, uint32_t frequency); 88 89 /* legacy pre qom */ 90 SerialState *serial_init(int base, qemu_irq irq, int baudbase, 91 Chardev *chr, MemoryRegion *system_io); 92 SerialState *serial_mm_init(MemoryRegion *address_space, 93 hwaddr base, int it_shift, 94 qemu_irq irq, int baudbase, 95 Chardev *chr, enum device_endian end); 96 97 /* serial-isa.c */ 98 99 #define MAX_ISA_SERIAL_PORTS 4 100 101 #define TYPE_ISA_SERIAL "isa-serial" 102 void serial_hds_isa_init(ISABus *bus, int from, int to); 103 104 #endif 105