xref: /openbmc/qemu/include/hw/char/serial.h (revision 2b74dd91)
1 /*
2  * QEMU 16550A UART emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2008 Citrix Systems, Inc.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #ifndef HW_SERIAL_H
27 #define HW_SERIAL_H
28 
29 #include "chardev/char-fe.h"
30 #include "exec/memory.h"
31 #include "qemu/fifo8.h"
32 #include "qom/object.h"
33 
34 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
35 
36 struct SerialState {
37     DeviceState parent;
38 
39     uint16_t divider;
40     uint8_t rbr; /* receive register */
41     uint8_t thr; /* transmit holding register */
42     uint8_t tsr; /* transmit shift register */
43     uint8_t ier;
44     uint8_t iir; /* read only */
45     uint8_t lcr;
46     uint8_t mcr;
47     uint8_t lsr; /* read only */
48     uint8_t msr; /* read only */
49     uint8_t scr;
50     uint8_t fcr;
51     uint8_t fcr_vmstate; /* we can't write directly this value
52                             it has side effects */
53     /* NOTE: this hidden state is necessary for tx irq generation as
54        it can be reset while reading iir */
55     int thr_ipending;
56     qemu_irq irq;
57     CharBackend chr;
58     int last_break_enable;
59     uint32_t baudbase;
60     uint32_t tsr_retry;
61     guint watch_tag;
62     bool wakeup;
63 
64     /* Time when the last byte was successfully sent out of the tsr */
65     uint64_t last_xmit_ts;
66     Fifo8 recv_fifo;
67     Fifo8 xmit_fifo;
68     /* Interrupt trigger level for recv_fifo */
69     uint8_t recv_fifo_itl;
70 
71     QEMUTimer *fifo_timeout_timer;
72     int timeout_ipending;           /* timeout interrupt pending state */
73 
74     uint64_t char_transmit_time;    /* time to transmit a char in ticks */
75     int poll_msl;
76 
77     QEMUTimer *modem_status_poll;
78     MemoryRegion io;
79 };
80 typedef struct SerialState SerialState;
81 
82 extern const VMStateDescription vmstate_serial;
83 extern const MemoryRegionOps serial_io_ops;
84 
85 #define TYPE_SERIAL "serial"
86 OBJECT_DECLARE_SIMPLE_TYPE(SerialState, SERIAL)
87 
88 #endif
89