1*a8fb0a50SBin Meng /*
2*a8fb0a50SBin Meng  * Microchip PolarFire SoC MMUART emulation
3*a8fb0a50SBin Meng  *
4*a8fb0a50SBin Meng  * Copyright (c) 2020 Wind River Systems, Inc.
5*a8fb0a50SBin Meng  *
6*a8fb0a50SBin Meng  * Author:
7*a8fb0a50SBin Meng  *   Bin Meng <bin.meng@windriver.com>
8*a8fb0a50SBin Meng  *
9*a8fb0a50SBin Meng  * Permission is hereby granted, free of charge, to any person obtaining a copy
10*a8fb0a50SBin Meng  * of this software and associated documentation files (the "Software"), to deal
11*a8fb0a50SBin Meng  * in the Software without restriction, including without limitation the rights
12*a8fb0a50SBin Meng  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13*a8fb0a50SBin Meng  * copies of the Software, and to permit persons to whom the Software is
14*a8fb0a50SBin Meng  * furnished to do so, subject to the following conditions:
15*a8fb0a50SBin Meng  *
16*a8fb0a50SBin Meng  * The above copyright notice and this permission notice shall be included in
17*a8fb0a50SBin Meng  * all copies or substantial portions of the Software.
18*a8fb0a50SBin Meng  *
19*a8fb0a50SBin Meng  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20*a8fb0a50SBin Meng  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21*a8fb0a50SBin Meng  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22*a8fb0a50SBin Meng  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23*a8fb0a50SBin Meng  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24*a8fb0a50SBin Meng  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25*a8fb0a50SBin Meng  * THE SOFTWARE.
26*a8fb0a50SBin Meng  */
27*a8fb0a50SBin Meng 
28*a8fb0a50SBin Meng #ifndef HW_MCHP_PFSOC_MMUART_H
29*a8fb0a50SBin Meng #define HW_MCHP_PFSOC_MMUART_H
30*a8fb0a50SBin Meng 
31*a8fb0a50SBin Meng #include "hw/char/serial.h"
32*a8fb0a50SBin Meng 
33*a8fb0a50SBin Meng #define MCHP_PFSOC_MMUART_REG_SIZE  52
34*a8fb0a50SBin Meng 
35*a8fb0a50SBin Meng typedef struct MchpPfSoCMMUartState {
36*a8fb0a50SBin Meng     MemoryRegion iomem;
37*a8fb0a50SBin Meng     hwaddr base;
38*a8fb0a50SBin Meng     qemu_irq irq;
39*a8fb0a50SBin Meng 
40*a8fb0a50SBin Meng     SerialMM *serial;
41*a8fb0a50SBin Meng 
42*a8fb0a50SBin Meng     uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
43*a8fb0a50SBin Meng } MchpPfSoCMMUartState;
44*a8fb0a50SBin Meng 
45*a8fb0a50SBin Meng /**
46*a8fb0a50SBin Meng  * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
47*a8fb0a50SBin Meng  *
48*a8fb0a50SBin Meng  * This is a helper routine for board to create a MMUART device that is
49*a8fb0a50SBin Meng  * compatible with Microchip PolarFire SoC.
50*a8fb0a50SBin Meng  *
51*a8fb0a50SBin Meng  * @sysmem: system memory region to map
52*a8fb0a50SBin Meng  * @base: base address of the MMUART registers
53*a8fb0a50SBin Meng  * @irq: IRQ number of the MMUART device
54*a8fb0a50SBin Meng  * @chr: character device to associate to
55*a8fb0a50SBin Meng  *
56*a8fb0a50SBin Meng  * @return: a pointer to the device specific control structure
57*a8fb0a50SBin Meng  */
58*a8fb0a50SBin Meng MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
59*a8fb0a50SBin Meng     hwaddr base, qemu_irq irq, Chardev *chr);
60*a8fb0a50SBin Meng 
61*a8fb0a50SBin Meng #endif /* HW_MCHP_PFSOC_MMUART_H */
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