1 /* 2 * Device model for i.MX UART 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef IMX_SERIAL_H 19 #define IMX_SERIAL_H 20 21 #include "hw/sysbus.h" 22 #include "chardev/char-fe.h" 23 #include "qom/object.h" 24 #include "qemu/fifo32.h" 25 26 #define TYPE_IMX_SERIAL "imx.serial" 27 OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) 28 29 #define FIFO_SIZE 32 30 31 #define URXD_CHARRDY (1<<15) /* character read is valid */ 32 #define URXD_ERR (1<<14) /* Character has error */ 33 #define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */ 34 #define URXD_FRMERR (1<<12) /* Character has frame error */ 35 #define URXD_BRK (1<<11) /* Break received */ 36 37 #define USR1_PARTYER (1<<15) /* Parity Error */ 38 #define USR1_RTSS (1<<14) /* RTS pin status */ 39 #define USR1_TRDY (1<<13) /* Tx ready */ 40 #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ 41 #define USR1_ESCF (1<<11) /* Escape sequence interrupt */ 42 #define USR1_FRAMERR (1<<10) /* Framing error */ 43 #define USR1_RRDY (1<<9) /* receiver ready */ 44 #define USR1_AGTIM (1<<8) /* Aging timer interrupt */ 45 #define USR1_DTRD (1<<7) /* DTR changed */ 46 #define USR1_RXDS (1<<6) /* Receiver is idle */ 47 #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ 48 #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ 49 50 #define USR2_ADET (1<<15) /* Autobaud complete */ 51 #define USR2_TXFE (1<<14) /* Transmit FIFO empty */ 52 #define USR2_DTRF (1<<13) /* DTR/DSR transition */ 53 #define USR2_IDLE (1<<12) /* UART has been idle for too long */ 54 #define USR2_ACST (1<<11) /* Autobaud counter stopped */ 55 #define USR2_RIDELT (1<<10) /* Ring Indicator delta */ 56 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 57 #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ 58 #define USR2_WAKE (1<<7) /* Start bit detected */ 59 #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ 60 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 61 #define USR2_RTSF (1<<4) /* RTS transition */ 62 #define USR2_TXDC (1<<3) /* Transmission complete */ 63 #define USR2_BRCD (1<<2) /* Break condition detected */ 64 #define USR2_ORE (1<<1) /* Overrun error */ 65 #define USR2_RDR (1<<0) /* Receive data ready */ 66 67 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ 68 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ 69 #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ 70 #define UCR1_UARTEN (1<<0) /* UART Enable */ 71 72 #define UCR2_ATEN (1<<3) /* Ageing Timer Enable */ 73 #define UCR2_TXEN (1<<2) /* Transmitter enable */ 74 #define UCR2_RXEN (1<<1) /* Receiver enable */ 75 #define UCR2_SRST (1<<0) /* Reset complete */ 76 77 #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ 78 #define UCR4_OREN BIT(1) /* Overrun interrupt enable */ 79 #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ 80 #define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ 81 82 #define UTS1_TXEMPTY (1<<6) 83 #define UTS1_RXEMPTY (1<<5) 84 #define UTS1_TXFULL (1<<4) 85 #define UTS1_RXFULL (1<<3) 86 87 #define TL_MASK 0x3f 88 89 /* Bit time in nanoseconds assuming maximum baud rate of 115200 */ 90 #define BIT_TIME_NS 8681 91 92 /* Assume 8 bits per character */ 93 #define NUM_BITS 8 94 95 /* Ageing timer triggers after 8 characters */ 96 #define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS) 97 98 struct IMXSerialState { 99 /*< private >*/ 100 SysBusDevice parent_obj; 101 102 /*< public >*/ 103 MemoryRegion iomem; 104 QEMUTimer ageing_timer; 105 Fifo32 rx_fifo; 106 107 uint32_t usr1; 108 uint32_t usr2; 109 uint32_t ucr1; 110 uint32_t ucr2; 111 uint32_t uts1; 112 113 /* 114 * The registers below are implemented just so that the 115 * guest OS sees what it has written 116 */ 117 uint32_t onems; 118 uint32_t ufcr; 119 uint32_t ubmr; 120 uint32_t ubrc; 121 uint32_t ucr3; 122 uint32_t ucr4; 123 124 qemu_irq irq; 125 CharBackend chr; 126 }; 127 128 #endif 129