1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef CADENCE_UART_H 20 #define CADENCE_UART_H 21 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "chardev/char-fe.h" 25 #include "qemu/timer.h" 26 27 #define CADENCE_UART_RX_FIFO_SIZE 16 28 #define CADENCE_UART_TX_FIFO_SIZE 16 29 30 #define CADENCE_UART_R_MAX (0x48/4) 31 32 #define TYPE_CADENCE_UART "cadence_uart" 33 #define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \ 34 TYPE_CADENCE_UART) 35 36 typedef struct { 37 /*< private >*/ 38 SysBusDevice parent_obj; 39 40 /*< public >*/ 41 MemoryRegion iomem; 42 uint32_t r[CADENCE_UART_R_MAX]; 43 uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE]; 44 uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE]; 45 uint32_t rx_wpos; 46 uint32_t rx_count; 47 uint32_t tx_count; 48 uint64_t char_tx_time; 49 CharBackend chr; 50 qemu_irq irq; 51 QEMUTimer *fifo_trigger_handle; 52 Clock *refclk; 53 } CadenceUARTState; 54 55 static inline DeviceState *cadence_uart_create(hwaddr addr, 56 qemu_irq irq, 57 Chardev *chr) 58 { 59 DeviceState *dev; 60 SysBusDevice *s; 61 62 dev = qdev_create(NULL, TYPE_CADENCE_UART); 63 s = SYS_BUS_DEVICE(dev); 64 qdev_prop_set_chr(dev, "chardev", chr); 65 qdev_init_nofail(dev); 66 sysbus_mmio_map(s, 0, addr); 67 sysbus_connect_irq(s, 0, irq); 68 69 return dev; 70 } 71 72 #endif 73