1 /* 2 * AVR USART 3 * 4 * Copyright (c) 2018 University of Kent 5 * Author: Sarah Harris 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #ifndef HW_CHAR_AVR_USART_H 23 #define HW_CHAR_AVR_USART_H 24 25 #include "hw/sysbus.h" 26 #include "chardev/char-fe.h" 27 #include "hw/hw.h" 28 #include "qom/object.h" 29 30 /* Offsets of registers. */ 31 #define USART_DR 0x06 32 #define USART_CSRA 0x00 33 #define USART_CSRB 0x01 34 #define USART_CSRC 0x02 35 #define USART_BRRH 0x05 36 #define USART_BRRL 0x04 37 38 /* Relevant bits in regiters. */ 39 #define USART_CSRA_RXC (1 << 7) 40 #define USART_CSRA_TXC (1 << 6) 41 #define USART_CSRA_DRE (1 << 5) 42 #define USART_CSRA_MPCM (1 << 0) 43 44 #define USART_CSRB_RXCIE (1 << 7) 45 #define USART_CSRB_TXCIE (1 << 6) 46 #define USART_CSRB_DREIE (1 << 5) 47 #define USART_CSRB_RXEN (1 << 4) 48 #define USART_CSRB_TXEN (1 << 3) 49 #define USART_CSRB_CSZ2 (1 << 2) 50 #define USART_CSRB_RXB8 (1 << 1) 51 #define USART_CSRB_TXB8 (1 << 0) 52 53 #define USART_CSRC_MSEL1 (1 << 7) 54 #define USART_CSRC_MSEL0 (1 << 6) 55 #define USART_CSRC_PM1 (1 << 5) 56 #define USART_CSRC_PM0 (1 << 4) 57 #define USART_CSRC_CSZ1 (1 << 2) 58 #define USART_CSRC_CSZ0 (1 << 1) 59 60 #define TYPE_AVR_USART "avr-usart" 61 typedef struct AVRUsartState AVRUsartState; 62 DECLARE_INSTANCE_CHECKER(AVRUsartState, AVR_USART, 63 TYPE_AVR_USART) 64 65 struct AVRUsartState { 66 /* <private> */ 67 SysBusDevice parent_obj; 68 69 /* <public> */ 70 MemoryRegion mmio; 71 72 CharBackend chr; 73 74 bool enabled; 75 76 uint8_t data; 77 bool data_valid; 78 uint8_t char_mask; 79 /* Control and Status Registers */ 80 uint8_t csra; 81 uint8_t csrb; 82 uint8_t csrc; 83 /* Baud Rate Registers (low/high byte) */ 84 uint8_t brrh; 85 uint8_t brrl; 86 87 /* Receive Complete */ 88 qemu_irq rxc_irq; 89 /* Transmit Complete */ 90 qemu_irq txc_irq; 91 /* Data Register Empty */ 92 qemu_irq dre_irq; 93 }; 94 95 #endif /* HW_CHAR_AVR_USART_H */ 96