1 #ifndef HW_FLASH_H 2 #define HW_FLASH_H 3 4 /* NOR flash devices */ 5 6 #include "exec/memory.h" 7 8 #define TYPE_CFI_PFLASH01 "cfi.pflash01" 9 #define TYPE_CFI_PFLASH02 "cfi.pflash02" 10 11 typedef struct pflash_t pflash_t; 12 13 /* pflash_cfi01.c */ 14 pflash_t *pflash_cfi01_register(hwaddr base, 15 DeviceState *qdev, const char *name, 16 hwaddr size, 17 BlockBackend *blk, 18 uint32_t sector_len, int nb_blocs, int width, 19 uint16_t id0, uint16_t id1, 20 uint16_t id2, uint16_t id3, int be); 21 22 /* pflash_cfi02.c */ 23 pflash_t *pflash_cfi02_register(hwaddr base, 24 DeviceState *qdev, const char *name, 25 hwaddr size, 26 BlockBackend *blk, uint32_t sector_len, 27 int nb_blocs, int nb_mappings, int width, 28 uint16_t id0, uint16_t id1, 29 uint16_t id2, uint16_t id3, 30 uint16_t unlock_addr0, uint16_t unlock_addr1, 31 int be); 32 33 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl); 34 35 /* nand.c */ 36 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); 37 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, 38 uint8_t ce, uint8_t wp, uint8_t gnd); 39 void nand_getpins(DeviceState *dev, int *rb); 40 void nand_setio(DeviceState *dev, uint32_t value); 41 uint32_t nand_getio(DeviceState *dev); 42 uint32_t nand_getbuswidth(DeviceState *dev); 43 44 #define NAND_MFR_TOSHIBA 0x98 45 #define NAND_MFR_SAMSUNG 0xec 46 #define NAND_MFR_FUJITSU 0x04 47 #define NAND_MFR_NATIONAL 0x8f 48 #define NAND_MFR_RENESAS 0x07 49 #define NAND_MFR_STMICRO 0x20 50 #define NAND_MFR_HYNIX 0xad 51 #define NAND_MFR_MICRON 0x2c 52 53 /* onenand.c */ 54 void *onenand_raw_otp(DeviceState *onenand_device); 55 56 /* ecc.c */ 57 typedef struct { 58 uint8_t cp; /* Column parity */ 59 uint16_t lp[2]; /* Line parity */ 60 uint16_t count; 61 } ECCState; 62 63 uint8_t ecc_digest(ECCState *s, uint8_t sample); 64 void ecc_reset(ECCState *s); 65 extern VMStateDescription vmstate_ecc_state; 66 67 #endif 68