xref: /openbmc/qemu/include/hw/arm/xlnx-zynqmp.h (revision b14df228)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #ifndef XLNX_ZYNQMP_H
19 #define XLNX_ZYNQMP_H
20 
21 #include "hw/arm/boot.h"
22 #include "hw/intc/arm_gic.h"
23 #include "hw/net/cadence_gem.h"
24 #include "hw/char/cadence_uart.h"
25 #include "hw/net/xlnx-zynqmp-can.h"
26 #include "hw/ide/ahci.h"
27 #include "hw/sd/sdhci.h"
28 #include "hw/ssi/xilinx_spips.h"
29 #include "hw/dma/xlnx_dpdma.h"
30 #include "hw/dma/xlnx-zdma.h"
31 #include "hw/display/xlnx_dp.h"
32 #include "hw/intc/xlnx-zynqmp-ipi.h"
33 #include "hw/rtc/xlnx-zynqmp-rtc.h"
34 #include "hw/cpu/cluster.h"
35 #include "target/arm/cpu.h"
36 #include "qom/object.h"
37 #include "net/can_emu.h"
38 #include "hw/dma/xlnx_csu_dma.h"
39 #include "hw/nvram/xlnx-bbram.h"
40 #include "hw/nvram/xlnx-zynqmp-efuse.h"
41 #include "hw/or-irq.h"
42 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
43 #include "hw/misc/xlnx-zynqmp-crf.h"
44 #include "hw/timer/cadence_ttc.h"
45 
46 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
47 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
48 
49 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
50 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
51 #define XLNX_ZYNQMP_NUM_GEMS 4
52 #define XLNX_ZYNQMP_NUM_UARTS 2
53 #define XLNX_ZYNQMP_NUM_CAN 2
54 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
55 #define XLNX_ZYNQMP_NUM_SDHCI 2
56 #define XLNX_ZYNQMP_NUM_SPIS 2
57 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
58 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
59 
60 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
61 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
62 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
63 
64 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
65 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
66 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
67 
68 #define XLNX_ZYNQMP_GIC_REGIONS 6
69 
70 /*
71  * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
72  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
73  * aligned address in the 64k region. To implement each GIC region needs a
74  * number of memory region aliases.
75  */
76 
77 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
78 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
79 
80 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
81 
82 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
83 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
84 
85 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
86                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
87 
88 #define XLNX_ZYNQMP_NUM_TTC 4
89 
90 /*
91  * Unimplemented mmio regions needed to boot some images.
92  */
93 #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
94 
95 struct XlnxZynqMPState {
96     /*< private >*/
97     DeviceState parent_obj;
98 
99     /*< public >*/
100     CPUClusterState apu_cluster;
101     CPUClusterState rpu_cluster;
102     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
103     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
104     GICState gic;
105     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
106 
107     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
108 
109     MemoryRegion *ddr_ram;
110     MemoryRegion ddr_ram_low, ddr_ram_high;
111     XlnxBBRam bbram;
112     XlnxEFuse efuse;
113     XlnxZynqMPEFuse efuse_ctrl;
114 
115     MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
116 
117     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
118     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
119     XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
120     SysbusAHCIState sata;
121     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
122     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
123     XlnxZynqMPQSPIPS qspi;
124     XlnxDPState dp;
125     XlnxDPDMAState dpdma;
126     XlnxZynqMPIPI ipi;
127     XlnxZynqMPRTC rtc;
128     XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
129     XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
130     XlnxCSUDMA qspi_dma;
131     qemu_or_irq qspi_irq_orgate;
132     XlnxZynqMPAPUCtrl apu_ctrl;
133     XlnxZynqMPCRF crf;
134     CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
135 
136     char *boot_cpu;
137     ARMCPU *boot_cpu_ptr;
138 
139     /* Has the ARM Security extensions?  */
140     bool secure;
141     /* Has the ARM Virtualization extensions?  */
142     bool virt;
143 
144     /* CAN bus. */
145     CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
146 };
147 
148 #endif
149