xref: /openbmc/qemu/include/hw/arm/xlnx-zynqmp.h (revision a003dbc6)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #ifndef XLNX_ZYNQMP_H
19 #define XLNX_ZYNQMP_H
20 
21 #include "hw/arm/boot.h"
22 #include "hw/intc/arm_gic.h"
23 #include "hw/net/cadence_gem.h"
24 #include "hw/char/cadence_uart.h"
25 #include "hw/net/xlnx-zynqmp-can.h"
26 #include "hw/ide/ahci.h"
27 #include "hw/sd/sdhci.h"
28 #include "hw/ssi/xilinx_spips.h"
29 #include "hw/dma/xlnx_dpdma.h"
30 #include "hw/dma/xlnx-zdma.h"
31 #include "hw/display/xlnx_dp.h"
32 #include "hw/intc/xlnx-zynqmp-ipi.h"
33 #include "hw/rtc/xlnx-zynqmp-rtc.h"
34 #include "hw/cpu/cluster.h"
35 #include "target/arm/cpu.h"
36 #include "qom/object.h"
37 #include "net/can_emu.h"
38 #include "hw/dma/xlnx_csu_dma.h"
39 
40 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
41 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
42 
43 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
44 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
45 #define XLNX_ZYNQMP_NUM_GEMS 4
46 #define XLNX_ZYNQMP_NUM_UARTS 2
47 #define XLNX_ZYNQMP_NUM_CAN 2
48 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
49 #define XLNX_ZYNQMP_NUM_SDHCI 2
50 #define XLNX_ZYNQMP_NUM_SPIS 2
51 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
52 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
53 
54 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
55 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
56 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
57 
58 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
59 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
60 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
61 
62 #define XLNX_ZYNQMP_GIC_REGIONS 6
63 
64 /*
65  * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
66  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
67  * aligned address in the 64k region. To implement each GIC region needs a
68  * number of memory region aliases.
69  */
70 
71 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
72 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
73 
74 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
75 
76 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
77 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
78 
79 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
80                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
81 
82 /*
83  * Unimplemented mmio regions needed to boot some images.
84  */
85 #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
86 
87 struct XlnxZynqMPState {
88     /*< private >*/
89     DeviceState parent_obj;
90 
91     /*< public >*/
92     CPUClusterState apu_cluster;
93     CPUClusterState rpu_cluster;
94     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
95     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
96     GICState gic;
97     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
98 
99     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
100 
101     MemoryRegion *ddr_ram;
102     MemoryRegion ddr_ram_low, ddr_ram_high;
103 
104     MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
105 
106     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
107     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
108     XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
109     SysbusAHCIState sata;
110     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
111     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
112     XlnxZynqMPQSPIPS qspi;
113     XlnxDPState dp;
114     XlnxDPDMAState dpdma;
115     XlnxZynqMPIPI ipi;
116     XlnxZynqMPRTC rtc;
117     XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
118     XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
119     XlnxCSUDMA qspi_dma;
120 
121     char *boot_cpu;
122     ARMCPU *boot_cpu_ptr;
123 
124     /* Has the ARM Security extensions?  */
125     bool secure;
126     /* Has the ARM Virtualization extensions?  */
127     bool virt;
128 
129     /* CAN bus. */
130     CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
131 };
132 
133 #endif
134