1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 #define XLNX_ZYNQMP_H 20 21 #include "hw/arm/boot.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/net/xlnx-zynqmp-can.h" 26 #include "hw/ide/ahci.h" 27 #include "hw/sd/sdhci.h" 28 #include "hw/ssi/xilinx_spips.h" 29 #include "hw/dma/xlnx_dpdma.h" 30 #include "hw/dma/xlnx-zdma.h" 31 #include "hw/display/xlnx_dp.h" 32 #include "hw/intc/xlnx-zynqmp-ipi.h" 33 #include "hw/rtc/xlnx-zynqmp-rtc.h" 34 #include "hw/cpu/cluster.h" 35 #include "target/arm/cpu.h" 36 #include "qom/object.h" 37 #include "net/can_emu.h" 38 #include "hw/dma/xlnx_csu_dma.h" 39 #include "hw/nvram/xlnx-bbram.h" 40 #include "hw/nvram/xlnx-zynqmp-efuse.h" 41 #include "hw/or-irq.h" 42 43 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" 44 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) 45 46 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 47 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 48 #define XLNX_ZYNQMP_NUM_GEMS 4 49 #define XLNX_ZYNQMP_NUM_UARTS 2 50 #define XLNX_ZYNQMP_NUM_CAN 2 51 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) 52 #define XLNX_ZYNQMP_NUM_SDHCI 2 53 #define XLNX_ZYNQMP_NUM_SPIS 2 54 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 55 #define XLNX_ZYNQMP_NUM_ADMA_CH 8 56 57 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 58 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 59 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 60 61 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 62 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 63 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 64 65 #define XLNX_ZYNQMP_GIC_REGIONS 6 66 67 /* 68 * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 69 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 70 * aligned address in the 64k region. To implement each GIC region needs a 71 * number of memory region aliases. 72 */ 73 74 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 75 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) 76 77 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 78 79 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 80 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 81 82 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 83 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 84 85 /* 86 * Unimplemented mmio regions needed to boot some images. 87 */ 88 #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 89 90 struct XlnxZynqMPState { 91 /*< private >*/ 92 DeviceState parent_obj; 93 94 /*< public >*/ 95 CPUClusterState apu_cluster; 96 CPUClusterState rpu_cluster; 97 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 98 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 99 GICState gic; 100 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 101 102 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 103 104 MemoryRegion *ddr_ram; 105 MemoryRegion ddr_ram_low, ddr_ram_high; 106 XlnxBBRam bbram; 107 XlnxEFuse efuse; 108 XlnxZynqMPEFuse efuse_ctrl; 109 110 MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; 111 112 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 113 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 114 XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; 115 SysbusAHCIState sata; 116 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 117 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; 118 XlnxZynqMPQSPIPS qspi; 119 XlnxDPState dp; 120 XlnxDPDMAState dpdma; 121 XlnxZynqMPIPI ipi; 122 XlnxZynqMPRTC rtc; 123 XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; 124 XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; 125 XlnxCSUDMA qspi_dma; 126 qemu_or_irq qspi_irq_orgate; 127 128 char *boot_cpu; 129 ARMCPU *boot_cpu_ptr; 130 131 /* Has the ARM Security extensions? */ 132 bool secure; 133 /* Has the ARM Virtualization extensions? */ 134 bool virt; 135 136 /* CAN bus. */ 137 CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; 138 }; 139 140 #endif 141