1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 #define XLNX_ZYNQMP_H 20 21 #include "hw/arm/boot.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/net/xlnx-zynqmp-can.h" 26 #include "hw/ide/ahci.h" 27 #include "hw/sd/sdhci.h" 28 #include "hw/ssi/xilinx_spips.h" 29 #include "hw/dma/xlnx_dpdma.h" 30 #include "hw/dma/xlnx-zdma.h" 31 #include "hw/display/xlnx_dp.h" 32 #include "hw/intc/xlnx-zynqmp-ipi.h" 33 #include "hw/rtc/xlnx-zynqmp-rtc.h" 34 #include "hw/cpu/cluster.h" 35 #include "target/arm/cpu.h" 36 #include "qom/object.h" 37 #include "net/can_emu.h" 38 #include "hw/dma/xlnx_csu_dma.h" 39 40 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" 41 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) 42 43 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 44 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 45 #define XLNX_ZYNQMP_NUM_GEMS 4 46 #define XLNX_ZYNQMP_NUM_UARTS 2 47 #define XLNX_ZYNQMP_NUM_CAN 2 48 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) 49 #define XLNX_ZYNQMP_NUM_SDHCI 2 50 #define XLNX_ZYNQMP_NUM_SPIS 2 51 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 52 #define XLNX_ZYNQMP_NUM_ADMA_CH 8 53 54 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 55 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 56 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 57 58 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 59 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 60 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 61 62 #define XLNX_ZYNQMP_GIC_REGIONS 6 63 64 /* 65 * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 66 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 67 * aligned address in the 64k region. To implement each GIC region needs a 68 * number of memory region aliases. 69 */ 70 71 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 72 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) 73 74 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 75 76 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 77 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 78 79 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 80 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 81 82 struct XlnxZynqMPState { 83 /*< private >*/ 84 DeviceState parent_obj; 85 86 /*< public >*/ 87 CPUClusterState apu_cluster; 88 CPUClusterState rpu_cluster; 89 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 90 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 91 GICState gic; 92 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 93 94 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 95 96 MemoryRegion *ddr_ram; 97 MemoryRegion ddr_ram_low, ddr_ram_high; 98 99 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 100 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 101 XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; 102 SysbusAHCIState sata; 103 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 104 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; 105 XlnxZynqMPQSPIPS qspi; 106 XlnxDPState dp; 107 XlnxDPDMAState dpdma; 108 XlnxZynqMPIPI ipi; 109 XlnxZynqMPRTC rtc; 110 XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; 111 XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; 112 XlnxCSUDMA qspi_dma; 113 114 char *boot_cpu; 115 ARMCPU *boot_cpu_ptr; 116 117 /* Has the ARM Security extensions? */ 118 bool secure; 119 /* Has the ARM Virtualization extensions? */ 120 bool virt; 121 122 /* CAN bus. */ 123 CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; 124 }; 125 126 #endif 127