1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 #define XLNX_ZYNQMP_H 20 21 #include "hw/arm/boot.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/ide/pci.h" 26 #include "hw/ide/ahci.h" 27 #include "hw/sd/sdhci.h" 28 #include "hw/ssi/xilinx_spips.h" 29 #include "hw/dma/xlnx_dpdma.h" 30 #include "hw/dma/xlnx-zdma.h" 31 #include "hw/display/xlnx_dp.h" 32 #include "hw/intc/xlnx-zynqmp-ipi.h" 33 #include "hw/timer/xlnx-zynqmp-rtc.h" 34 #include "hw/cpu/cluster.h" 35 36 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 37 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 38 TYPE_XLNX_ZYNQMP) 39 40 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 41 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 42 #define XLNX_ZYNQMP_NUM_GEMS 4 43 #define XLNX_ZYNQMP_NUM_UARTS 2 44 #define XLNX_ZYNQMP_NUM_SDHCI 2 45 #define XLNX_ZYNQMP_NUM_SPIS 2 46 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 47 #define XLNX_ZYNQMP_NUM_ADMA_CH 8 48 49 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 50 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 51 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 52 53 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 54 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 55 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 56 57 #define XLNX_ZYNQMP_GIC_REGIONS 6 58 59 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 60 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 61 * aligned address in the 64k region. To implement each GIC region needs a 62 * number of memory region aliases. 63 */ 64 65 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 66 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) 67 68 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 69 70 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 71 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 72 73 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 74 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 75 76 typedef struct XlnxZynqMPState { 77 /*< private >*/ 78 DeviceState parent_obj; 79 80 /*< public >*/ 81 CPUClusterState apu_cluster; 82 CPUClusterState rpu_cluster; 83 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 84 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 85 GICState gic; 86 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 87 88 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 89 90 MemoryRegion *ddr_ram; 91 MemoryRegion ddr_ram_low, ddr_ram_high; 92 93 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 94 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 95 SysbusAHCIState sata; 96 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 97 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; 98 XlnxZynqMPQSPIPS qspi; 99 XlnxDPState dp; 100 XlnxDPDMAState dpdma; 101 XlnxZynqMPIPI ipi; 102 XlnxZynqMPRTC rtc; 103 XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; 104 XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; 105 106 char *boot_cpu; 107 ARMCPU *boot_cpu_ptr; 108 109 /* Has the ARM Security extensions? */ 110 bool secure; 111 /* Has the ARM Virtualization extensions? */ 112 bool virt; 113 /* Has the RPU subsystem? */ 114 bool has_rpu; 115 } XlnxZynqMPState; 116 117 #endif 118