1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 20 #include "qemu-common.h" 21 #include "hw/arm/arm.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/ide/pci.h" 26 #include "hw/ide/ahci.h" 27 #include "hw/sd/sdhci.h" 28 29 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 30 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 31 TYPE_XLNX_ZYNQMP) 32 33 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 34 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 35 #define XLNX_ZYNQMP_NUM_GEMS 4 36 #define XLNX_ZYNQMP_NUM_UARTS 2 37 #define XLNX_ZYNQMP_NUM_SDHCI 2 38 39 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 40 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 41 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 42 43 #define XLNX_ZYNQMP_GIC_REGIONS 2 44 45 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 46 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 47 * aligned address in the 64k region. To implement each GIC region needs a 48 * number of memory region aliases. 49 */ 50 51 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 52 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 53 54 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 55 56 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 57 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 58 59 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 60 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 61 62 typedef struct XlnxZynqMPState { 63 /*< private >*/ 64 DeviceState parent_obj; 65 66 /*< public >*/ 67 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 68 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 69 GICState gic; 70 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 71 72 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 73 74 MemoryRegion *ddr_ram; 75 MemoryRegion ddr_ram_low, ddr_ram_high; 76 77 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 78 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 79 SysbusAHCIState sata; 80 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 81 82 char *boot_cpu; 83 ARMCPU *boot_cpu_ptr; 84 } XlnxZynqMPState; 85 86 #define XLNX_ZYNQMP_H 87 #endif 88