1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 20 #include "qemu-common.h" 21 #include "hw/arm/arm.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 26 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 27 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 28 TYPE_XLNX_ZYNQMP) 29 30 #define XLNX_ZYNQMP_NUM_CPUS 4 31 #define XLNX_ZYNQMP_NUM_GEMS 4 32 #define XLNX_ZYNQMP_NUM_UARTS 2 33 34 #define XLNX_ZYNQMP_GIC_REGIONS 2 35 36 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 37 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 38 * aligned address in the 64k region. To implement each GIC region needs a 39 * number of memory region aliases. 40 */ 41 42 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000 43 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 44 45 typedef struct XlnxZynqMPState { 46 /*< private >*/ 47 DeviceState parent_obj; 48 49 /*< public >*/ 50 ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; 51 GICState gic; 52 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 53 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 54 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 55 } XlnxZynqMPState; 56 57 #define XLNX_ZYNQMP_H 58 #endif 59