xref: /openbmc/qemu/include/hw/arm/xlnx-zynqmp.h (revision 05caa062)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #ifndef XLNX_ZYNQMP_H
19 #define XLNX_ZYNQMP_H
20 
21 #include "hw/intc/arm_gic.h"
22 #include "hw/net/cadence_gem.h"
23 #include "hw/char/cadence_uart.h"
24 #include "hw/net/xlnx-zynqmp-can.h"
25 #include "hw/ide/ahci-sysbus.h"
26 #include "hw/sd/sdhci.h"
27 #include "hw/ssi/xilinx_spips.h"
28 #include "hw/dma/xlnx_dpdma.h"
29 #include "hw/dma/xlnx-zdma.h"
30 #include "hw/display/xlnx_dp.h"
31 #include "hw/intc/xlnx-zynqmp-ipi.h"
32 #include "hw/rtc/xlnx-zynqmp-rtc.h"
33 #include "hw/cpu/cluster.h"
34 #include "target/arm/cpu.h"
35 #include "qom/object.h"
36 #include "net/can_emu.h"
37 #include "hw/dma/xlnx_csu_dma.h"
38 #include "hw/nvram/xlnx-bbram.h"
39 #include "hw/nvram/xlnx-zynqmp-efuse.h"
40 #include "hw/or-irq.h"
41 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
42 #include "hw/misc/xlnx-zynqmp-crf.h"
43 #include "hw/timer/cadence_ttc.h"
44 #include "hw/usb/hcd-dwc3.h"
45 
46 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
47 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
48 
49 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
50 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
51 #define XLNX_ZYNQMP_NUM_GEMS 4
52 #define XLNX_ZYNQMP_NUM_UARTS 2
53 #define XLNX_ZYNQMP_NUM_CAN 2
54 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
55 #define XLNX_ZYNQMP_NUM_SDHCI 2
56 #define XLNX_ZYNQMP_NUM_SPIS 2
57 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
58 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
59 #define XLNX_ZYNQMP_NUM_USB 2
60 
61 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
62 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
63 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
64 
65 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
66 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
67 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
68 
69 #define XLNX_ZYNQMP_GIC_REGIONS 6
70 
71 /*
72  * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
73  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
74  * aligned address in the 64k region. To implement each GIC region needs a
75  * number of memory region aliases.
76  */
77 
78 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
79 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
80 
81 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
82 
83 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
84 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
85 
86 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
87                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
88 
89 #define XLNX_ZYNQMP_NUM_TTC 4
90 
91 /*
92  * Unimplemented mmio regions needed to boot some images.
93  */
94 #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
95 
96 struct XlnxZynqMPState {
97     /*< private >*/
98     DeviceState parent_obj;
99 
100     /*< public >*/
101     CPUClusterState apu_cluster;
102     CPUClusterState rpu_cluster;
103     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
104     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
105     GICState gic;
106     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
107 
108     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
109 
110     MemoryRegion *ddr_ram;
111     MemoryRegion ddr_ram_low, ddr_ram_high;
112     XlnxBBRam bbram;
113     XlnxEFuse efuse;
114     XlnxZynqMPEFuse efuse_ctrl;
115 
116     MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
117 
118     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
119     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
120     XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
121     SysbusAHCIState sata;
122     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
123     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
124     XlnxZynqMPQSPIPS qspi;
125     XlnxDPState dp;
126     XlnxDPDMAState dpdma;
127     XlnxZynqMPIPI ipi;
128     XlnxZynqMPRTC rtc;
129     XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
130     XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
131     XlnxCSUDMA qspi_dma;
132     OrIRQState qspi_irq_orgate;
133     XlnxZynqMPAPUCtrl apu_ctrl;
134     XlnxZynqMPCRF crf;
135     CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
136     USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
137 
138     char *boot_cpu;
139     ARMCPU *boot_cpu_ptr;
140 
141     /* Has the ARM Security extensions?  */
142     bool secure;
143     /* Has the ARM Virtualization extensions?  */
144     bool virt;
145 
146     /* CAN bus. */
147     CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
148 };
149 
150 #endif
151