xref: /openbmc/qemu/include/hw/arm/xlnx-versal.h (revision dfc86c0f)
1 /*
2  * Model of the Xilinx Versal
3  *
4  * Copyright (c) 2018 Xilinx Inc.
5  * Written by Edgar E. Iglesias
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 or
9  * (at your option) any later version.
10  */
11 
12 #ifndef XLNX_VERSAL_H
13 #define XLNX_VERSAL_H
14 
15 #include "hw/sysbus.h"
16 #include "hw/arm/boot.h"
17 #include "hw/or-irq.h"
18 #include "hw/sd/sdhci.h"
19 #include "hw/intc/arm_gicv3.h"
20 #include "hw/char/pl011.h"
21 #include "hw/dma/xlnx-zdma.h"
22 #include "hw/net/cadence_gem.h"
23 #include "hw/rtc/xlnx-zynqmp-rtc.h"
24 #include "qom/object.h"
25 #include "hw/usb/xlnx-usb-subsystem.h"
26 #include "hw/misc/xlnx-versal-xramc.h"
27 
28 #define TYPE_XLNX_VERSAL "xlnx-versal"
29 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
30 
31 #define XLNX_VERSAL_NR_ACPUS   2
32 #define XLNX_VERSAL_NR_UARTS   2
33 #define XLNX_VERSAL_NR_GEMS    2
34 #define XLNX_VERSAL_NR_ADMAS   8
35 #define XLNX_VERSAL_NR_SDS     2
36 #define XLNX_VERSAL_NR_XRAM    4
37 #define XLNX_VERSAL_NR_IRQS    192
38 
39 struct Versal {
40     /*< private >*/
41     SysBusDevice parent_obj;
42 
43     /*< public >*/
44     struct {
45         struct {
46             MemoryRegion mr;
47             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
48             GICv3State gic;
49         } apu;
50     } fpd;
51 
52     MemoryRegion mr_ps;
53 
54     struct {
55         /* 4 ranges to access DDR.  */
56         MemoryRegion mr_ddr_ranges[4];
57     } noc;
58 
59     struct {
60         MemoryRegion mr_ocm;
61 
62         struct {
63             PL011State uart[XLNX_VERSAL_NR_UARTS];
64             CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
65             XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
66             VersalUsb2 usb;
67         } iou;
68 
69         struct {
70             qemu_or_irq irq_orgate;
71             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
72         } xram;
73     } lpd;
74 
75     /* The Platform Management Controller subsystem.  */
76     struct {
77         struct {
78             SDHCIState sd[XLNX_VERSAL_NR_SDS];
79         } iou;
80 
81         XlnxZynqMPRTC rtc;
82     } pmc;
83 
84     struct {
85         MemoryRegion *mr_ddr;
86         uint32_t psci_conduit;
87     } cfg;
88 };
89 
90 /* Memory-map and IRQ definitions. Copied a subset from
91  * auto-generated files.  */
92 
93 #define VERSAL_GIC_MAINT_IRQ        9
94 #define VERSAL_TIMER_VIRT_IRQ       11
95 #define VERSAL_TIMER_S_EL1_IRQ      13
96 #define VERSAL_TIMER_NS_EL1_IRQ     14
97 #define VERSAL_TIMER_NS_EL2_IRQ     10
98 
99 #define VERSAL_UART0_IRQ_0         18
100 #define VERSAL_UART1_IRQ_0         19
101 #define VERSAL_USB0_IRQ_0          22
102 #define VERSAL_GEM0_IRQ_0          56
103 #define VERSAL_GEM0_WAKE_IRQ_0     57
104 #define VERSAL_GEM1_IRQ_0          58
105 #define VERSAL_GEM1_WAKE_IRQ_0     59
106 #define VERSAL_ADMA_IRQ_0          60
107 #define VERSAL_XRAM_IRQ_0          79
108 #define VERSAL_RTC_APB_ERR_IRQ     121
109 #define VERSAL_SD0_IRQ_0           126
110 #define VERSAL_RTC_ALARM_IRQ       142
111 #define VERSAL_RTC_SECONDS_IRQ     143
112 
113 /* Architecturally reserved IRQs suitable for virtualization.  */
114 #define VERSAL_RSVD_IRQ_FIRST 111
115 #define VERSAL_RSVD_IRQ_LAST  118
116 
117 #define MM_TOP_RSVD                 0xa0000000U
118 #define MM_TOP_RSVD_SIZE            0x4000000
119 #define MM_GIC_APU_DIST_MAIN        0xf9000000U
120 #define MM_GIC_APU_DIST_MAIN_SIZE   0x10000
121 #define MM_GIC_APU_REDIST_0         0xf9080000U
122 #define MM_GIC_APU_REDIST_0_SIZE    0x80000
123 
124 #define MM_UART0                    0xff000000U
125 #define MM_UART0_SIZE               0x10000
126 #define MM_UART1                    0xff010000U
127 #define MM_UART1_SIZE               0x10000
128 
129 #define MM_GEM0                     0xff0c0000U
130 #define MM_GEM0_SIZE                0x10000
131 #define MM_GEM1                     0xff0d0000U
132 #define MM_GEM1_SIZE                0x10000
133 
134 #define MM_ADMA_CH0                 0xffa80000U
135 #define MM_ADMA_CH0_SIZE            0x10000
136 
137 #define MM_OCM                      0xfffc0000U
138 #define MM_OCM_SIZE                 0x40000
139 
140 #define MM_XRAM                     0xfe800000
141 #define MM_XRAMC                    0xff8e0000
142 #define MM_XRAMC_SIZE               0x10000
143 
144 #define MM_USB2_CTRL_REGS           0xFF9D0000
145 #define MM_USB2_CTRL_REGS_SIZE      0x10000
146 
147 #define MM_USB_0                    0xFE200000
148 #define MM_USB_0_SIZE               0x10000
149 
150 #define MM_TOP_DDR                  0x0
151 #define MM_TOP_DDR_SIZE             0x80000000U
152 #define MM_TOP_DDR_2                0x800000000ULL
153 #define MM_TOP_DDR_2_SIZE           0x800000000ULL
154 #define MM_TOP_DDR_3                0xc000000000ULL
155 #define MM_TOP_DDR_3_SIZE           0x4000000000ULL
156 #define MM_TOP_DDR_4                0x10000000000ULL
157 #define MM_TOP_DDR_4_SIZE           0xb780000000ULL
158 
159 #define MM_PSM_START                0xffc80000U
160 #define MM_PSM_END                  0xffcf0000U
161 
162 #define MM_CRL                      0xff5e0000U
163 #define MM_CRL_SIZE                 0x300000
164 #define MM_IOU_SCNTR                0xff130000U
165 #define MM_IOU_SCNTR_SIZE           0x10000
166 #define MM_IOU_SCNTRS               0xff140000U
167 #define MM_IOU_SCNTRS_SIZE          0x10000
168 #define MM_FPD_CRF                  0xfd1a0000U
169 #define MM_FPD_CRF_SIZE             0x140000
170 #define MM_FPD_FPD_APU              0xfd5c0000
171 #define MM_FPD_FPD_APU_SIZE         0x100
172 
173 #define MM_PMC_SD0                  0xf1040000U
174 #define MM_PMC_SD0_SIZE             0x10000
175 #define MM_PMC_CRP                  0xf1260000U
176 #define MM_PMC_CRP_SIZE             0x10000
177 #define MM_PMC_RTC                  0xf12a0000
178 #define MM_PMC_RTC_SIZE             0x10000
179 #endif
180