1 /* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #ifndef XLNX_VERSAL_H 13 #define XLNX_VERSAL_H 14 15 #include "hw/sysbus.h" 16 #include "hw/cpu/cluster.h" 17 #include "hw/or-irq.h" 18 #include "hw/sd/sdhci.h" 19 #include "hw/intc/arm_gicv3.h" 20 #include "hw/char/pl011.h" 21 #include "hw/dma/xlnx-zdma.h" 22 #include "hw/net/cadence_gem.h" 23 #include "hw/rtc/xlnx-zynqmp-rtc.h" 24 #include "qom/object.h" 25 #include "hw/usb/xlnx-usb-subsystem.h" 26 #include "hw/misc/xlnx-versal-xramc.h" 27 #include "hw/nvram/xlnx-bbram.h" 28 #include "hw/nvram/xlnx-versal-efuse.h" 29 #include "hw/ssi/xlnx-versal-ospi.h" 30 #include "hw/dma/xlnx_csu_dma.h" 31 #include "hw/misc/xlnx-versal-crl.h" 32 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 33 #include "hw/misc/xlnx-versal-trng.h" 34 #include "hw/net/xlnx-versal-canfd.h" 35 #include "hw/misc/xlnx-versal-cfu.h" 36 #include "hw/misc/xlnx-versal-cframe-reg.h" 37 38 #define TYPE_XLNX_VERSAL "xlnx-versal" 39 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 40 41 #define XLNX_VERSAL_NR_ACPUS 2 42 #define XLNX_VERSAL_NR_RCPUS 2 43 #define XLNX_VERSAL_NR_UARTS 2 44 #define XLNX_VERSAL_NR_GEMS 2 45 #define XLNX_VERSAL_NR_ADMAS 8 46 #define XLNX_VERSAL_NR_SDS 2 47 #define XLNX_VERSAL_NR_XRAM 4 48 #define XLNX_VERSAL_NR_IRQS 192 49 #define XLNX_VERSAL_NR_CANFD 2 50 #define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000) 51 #define XLNX_VERSAL_NR_CFRAME 15 52 53 struct Versal { 54 /*< private >*/ 55 SysBusDevice parent_obj; 56 57 /*< public >*/ 58 struct { 59 struct { 60 MemoryRegion mr; 61 CPUClusterState cluster; 62 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 63 GICv3State gic; 64 } apu; 65 } fpd; 66 67 MemoryRegion mr_ps; 68 69 struct { 70 /* 4 ranges to access DDR. */ 71 MemoryRegion mr_ddr_ranges[4]; 72 } noc; 73 74 struct { 75 MemoryRegion mr_ocm; 76 77 struct { 78 PL011State uart[XLNX_VERSAL_NR_UARTS]; 79 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 80 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 81 VersalUsb2 usb; 82 CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 83 XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD]; 84 } iou; 85 86 /* Real-time Processing Unit. */ 87 struct { 88 MemoryRegion mr; 89 MemoryRegion mr_ps_alias; 90 91 CPUClusterState cluster; 92 ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; 93 } rpu; 94 95 struct { 96 OrIRQState irq_orgate; 97 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 98 } xram; 99 100 XlnxVersalCRL crl; 101 } lpd; 102 103 /* The Platform Management Controller subsystem. */ 104 struct { 105 struct { 106 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 107 XlnxVersalPmcIouSlcr slcr; 108 109 struct { 110 XlnxVersalOspi ospi; 111 XlnxCSUDMA dma_src; 112 XlnxCSUDMA dma_dst; 113 MemoryRegion linear_mr; 114 OrIRQState irq_orgate; 115 } ospi; 116 } iou; 117 118 XlnxZynqMPRTC rtc; 119 XlnxVersalTRng trng; 120 XlnxBBRam bbram; 121 XlnxEFuse efuse; 122 XlnxVersalEFuseCtrl efuse_ctrl; 123 XlnxVersalEFuseCache efuse_cache; 124 XlnxVersalCFUAPB cfu_apb; 125 XlnxVersalCFUFDRO cfu_fdro; 126 XlnxVersalCFUSFR cfu_sfr; 127 XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME]; 128 XlnxVersalCFrameBcastReg cframe_bcast; 129 130 OrIRQState apb_irq_orgate; 131 } pmc; 132 133 struct { 134 MemoryRegion *mr_ddr; 135 } cfg; 136 }; 137 138 /* Memory-map and IRQ definitions. Copied a subset from 139 * auto-generated files. */ 140 141 #define VERSAL_GIC_MAINT_IRQ 9 142 #define VERSAL_TIMER_VIRT_IRQ 11 143 #define VERSAL_TIMER_S_EL1_IRQ 13 144 #define VERSAL_TIMER_NS_EL1_IRQ 14 145 #define VERSAL_TIMER_NS_EL2_IRQ 10 146 147 #define VERSAL_CRL_IRQ 10 148 #define VERSAL_UART0_IRQ_0 18 149 #define VERSAL_UART1_IRQ_0 19 150 #define VERSAL_CANFD0_IRQ_0 20 151 #define VERSAL_CANFD1_IRQ_0 21 152 #define VERSAL_USB0_IRQ_0 22 153 #define VERSAL_GEM0_IRQ_0 56 154 #define VERSAL_GEM0_WAKE_IRQ_0 57 155 #define VERSAL_GEM1_IRQ_0 58 156 #define VERSAL_GEM1_WAKE_IRQ_0 59 157 #define VERSAL_ADMA_IRQ_0 60 158 #define VERSAL_XRAM_IRQ_0 79 159 #define VERSAL_CFU_IRQ_0 120 160 #define VERSAL_PMC_APB_IRQ 121 161 #define VERSAL_OSPI_IRQ 124 162 #define VERSAL_SD0_IRQ_0 126 163 #define VERSAL_EFUSE_IRQ 139 164 #define VERSAL_TRNG_IRQ 141 165 #define VERSAL_RTC_ALARM_IRQ 142 166 #define VERSAL_RTC_SECONDS_IRQ 143 167 168 /* Architecturally reserved IRQs suitable for virtualization. */ 169 #define VERSAL_RSVD_IRQ_FIRST 111 170 #define VERSAL_RSVD_IRQ_LAST 118 171 172 #define MM_TOP_RSVD 0xa0000000U 173 #define MM_TOP_RSVD_SIZE 0x4000000 174 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 175 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 176 #define MM_GIC_APU_REDIST_0 0xf9080000U 177 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 178 179 #define MM_UART0 0xff000000U 180 #define MM_UART0_SIZE 0x10000 181 #define MM_UART1 0xff010000U 182 #define MM_UART1_SIZE 0x10000 183 184 #define MM_CANFD0 0xff060000U 185 #define MM_CANFD0_SIZE 0x10000 186 #define MM_CANFD1 0xff070000U 187 #define MM_CANFD1_SIZE 0x10000 188 189 #define MM_GEM0 0xff0c0000U 190 #define MM_GEM0_SIZE 0x10000 191 #define MM_GEM1 0xff0d0000U 192 #define MM_GEM1_SIZE 0x10000 193 194 #define MM_ADMA_CH0 0xffa80000U 195 #define MM_ADMA_CH0_SIZE 0x10000 196 197 #define MM_OCM 0xfffc0000U 198 #define MM_OCM_SIZE 0x40000 199 200 #define MM_XRAM 0xfe800000 201 #define MM_XRAMC 0xff8e0000 202 #define MM_XRAMC_SIZE 0x10000 203 204 #define MM_USB2_CTRL_REGS 0xFF9D0000 205 #define MM_USB2_CTRL_REGS_SIZE 0x10000 206 207 #define MM_USB_0 0xFE200000 208 #define MM_USB_0_SIZE 0x10000 209 210 #define MM_TOP_DDR 0x0 211 #define MM_TOP_DDR_SIZE 0x80000000U 212 #define MM_TOP_DDR_2 0x800000000ULL 213 #define MM_TOP_DDR_2_SIZE 0x800000000ULL 214 #define MM_TOP_DDR_3 0xc000000000ULL 215 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 216 #define MM_TOP_DDR_4 0x10000000000ULL 217 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 218 219 #define MM_PSM_START 0xffc80000U 220 #define MM_PSM_END 0xffcf0000U 221 222 #define MM_CRL 0xff5e0000U 223 #define MM_CRL_SIZE 0x300000 224 #define MM_IOU_SCNTR 0xff130000U 225 #define MM_IOU_SCNTR_SIZE 0x10000 226 #define MM_IOU_SCNTRS 0xff140000U 227 #define MM_IOU_SCNTRS_SIZE 0x10000 228 #define MM_FPD_CRF 0xfd1a0000U 229 #define MM_FPD_CRF_SIZE 0x140000 230 #define MM_FPD_FPD_APU 0xfd5c0000 231 #define MM_FPD_FPD_APU_SIZE 0x100 232 233 #define MM_PMC_PMC_IOU_SLCR 0xf1060000 234 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 235 236 #define MM_PMC_OSPI 0xf1010000 237 #define MM_PMC_OSPI_SIZE 0x10000 238 239 #define MM_PMC_OSPI_DAC 0xc0000000 240 #define MM_PMC_OSPI_DAC_SIZE 0x20000000 241 242 #define MM_PMC_OSPI_DMA_DST 0xf1011800 243 #define MM_PMC_OSPI_DMA_SRC 0xf1011000 244 245 #define MM_PMC_SD0 0xf1040000U 246 #define MM_PMC_SD0_SIZE 0x10000 247 #define MM_PMC_BBRAM_CTRL 0xf11f0000 248 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 249 #define MM_PMC_EFUSE_CTRL 0xf1240000 250 #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 251 #define MM_PMC_EFUSE_CACHE 0xf1250000 252 #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 253 254 #define MM_PMC_CFU_APB 0xf12b0000 255 #define MM_PMC_CFU_APB_SIZE 0x10000 256 #define MM_PMC_CFU_STREAM 0xf12c0000 257 #define MM_PMC_CFU_STREAM_SIZE 0x1000 258 #define MM_PMC_CFU_SFR 0xf12c1000 259 #define MM_PMC_CFU_SFR_SIZE 0x1000 260 #define MM_PMC_CFU_FDRO 0xf12c2000 261 #define MM_PMC_CFU_FDRO_SIZE 0x1000 262 #define MM_PMC_CFU_STREAM_2 0xf1f80000 263 #define MM_PMC_CFU_STREAM_2_SIZE 0x40000 264 265 #define MM_PMC_CFRAME0_REG 0xf12d0000 266 #define MM_PMC_CFRAME0_REG_SIZE 0x1000 267 #define MM_PMC_CFRAME0_FDRI 0xf12d1000 268 #define MM_PMC_CFRAME0_FDRI_SIZE 0x1000 269 #define MM_PMC_CFRAME1_REG 0xf12d2000 270 #define MM_PMC_CFRAME1_REG_SIZE 0x1000 271 #define MM_PMC_CFRAME1_FDRI 0xf12d3000 272 #define MM_PMC_CFRAME1_FDRI_SIZE 0x1000 273 #define MM_PMC_CFRAME2_REG 0xf12d4000 274 #define MM_PMC_CFRAME2_REG_SIZE 0x1000 275 #define MM_PMC_CFRAME2_FDRI 0xf12d5000 276 #define MM_PMC_CFRAME2_FDRI_SIZE 0x1000 277 #define MM_PMC_CFRAME3_REG 0xf12d6000 278 #define MM_PMC_CFRAME3_REG_SIZE 0x1000 279 #define MM_PMC_CFRAME3_FDRI 0xf12d7000 280 #define MM_PMC_CFRAME3_FDRI_SIZE 0x1000 281 #define MM_PMC_CFRAME4_REG 0xf12d8000 282 #define MM_PMC_CFRAME4_REG_SIZE 0x1000 283 #define MM_PMC_CFRAME4_FDRI 0xf12d9000 284 #define MM_PMC_CFRAME4_FDRI_SIZE 0x1000 285 #define MM_PMC_CFRAME5_REG 0xf12da000 286 #define MM_PMC_CFRAME5_REG_SIZE 0x1000 287 #define MM_PMC_CFRAME5_FDRI 0xf12db000 288 #define MM_PMC_CFRAME5_FDRI_SIZE 0x1000 289 #define MM_PMC_CFRAME6_REG 0xf12dc000 290 #define MM_PMC_CFRAME6_REG_SIZE 0x1000 291 #define MM_PMC_CFRAME6_FDRI 0xf12dd000 292 #define MM_PMC_CFRAME6_FDRI_SIZE 0x1000 293 #define MM_PMC_CFRAME7_REG 0xf12de000 294 #define MM_PMC_CFRAME7_REG_SIZE 0x1000 295 #define MM_PMC_CFRAME7_FDRI 0xf12df000 296 #define MM_PMC_CFRAME7_FDRI_SIZE 0x1000 297 #define MM_PMC_CFRAME8_REG 0xf12e0000 298 #define MM_PMC_CFRAME8_REG_SIZE 0x1000 299 #define MM_PMC_CFRAME8_FDRI 0xf12e1000 300 #define MM_PMC_CFRAME8_FDRI_SIZE 0x1000 301 #define MM_PMC_CFRAME9_REG 0xf12e2000 302 #define MM_PMC_CFRAME9_REG_SIZE 0x1000 303 #define MM_PMC_CFRAME9_FDRI 0xf12e3000 304 #define MM_PMC_CFRAME9_FDRI_SIZE 0x1000 305 #define MM_PMC_CFRAME10_REG 0xf12e4000 306 #define MM_PMC_CFRAME10_REG_SIZE 0x1000 307 #define MM_PMC_CFRAME10_FDRI 0xf12e5000 308 #define MM_PMC_CFRAME10_FDRI_SIZE 0x1000 309 #define MM_PMC_CFRAME11_REG 0xf12e6000 310 #define MM_PMC_CFRAME11_REG_SIZE 0x1000 311 #define MM_PMC_CFRAME11_FDRI 0xf12e7000 312 #define MM_PMC_CFRAME11_FDRI_SIZE 0x1000 313 #define MM_PMC_CFRAME12_REG 0xf12e8000 314 #define MM_PMC_CFRAME12_REG_SIZE 0x1000 315 #define MM_PMC_CFRAME12_FDRI 0xf12e9000 316 #define MM_PMC_CFRAME12_FDRI_SIZE 0x1000 317 #define MM_PMC_CFRAME13_REG 0xf12ea000 318 #define MM_PMC_CFRAME13_REG_SIZE 0x1000 319 #define MM_PMC_CFRAME13_FDRI 0xf12eb000 320 #define MM_PMC_CFRAME13_FDRI_SIZE 0x1000 321 #define MM_PMC_CFRAME14_REG 0xf12ec000 322 #define MM_PMC_CFRAME14_REG_SIZE 0x1000 323 #define MM_PMC_CFRAME14_FDRI 0xf12ed000 324 #define MM_PMC_CFRAME14_FDRI_SIZE 0x1000 325 #define MM_PMC_CFRAME_BCAST_REG 0xf12ee000 326 #define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000 327 #define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000 328 #define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000 329 330 #define MM_PMC_CRP 0xf1260000U 331 #define MM_PMC_CRP_SIZE 0x10000 332 #define MM_PMC_RTC 0xf12a0000 333 #define MM_PMC_RTC_SIZE 0x10000 334 #define MM_PMC_TRNG 0xf1230000 335 #define MM_PMC_TRNG_SIZE 0x10000 336 #endif 337