1 /* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #ifndef XLNX_VERSAL_H 13 #define XLNX_VERSAL_H 14 15 #include "hw/sysbus.h" 16 #include "hw/arm/boot.h" 17 #include "hw/cpu/cluster.h" 18 #include "hw/or-irq.h" 19 #include "hw/sd/sdhci.h" 20 #include "hw/intc/arm_gicv3.h" 21 #include "hw/char/pl011.h" 22 #include "hw/dma/xlnx-zdma.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/rtc/xlnx-zynqmp-rtc.h" 25 #include "qom/object.h" 26 #include "hw/usb/xlnx-usb-subsystem.h" 27 #include "hw/misc/xlnx-versal-xramc.h" 28 #include "hw/nvram/xlnx-bbram.h" 29 #include "hw/nvram/xlnx-versal-efuse.h" 30 #include "hw/ssi/xlnx-versal-ospi.h" 31 #include "hw/dma/xlnx_csu_dma.h" 32 #include "hw/misc/xlnx-versal-crl.h" 33 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 34 #include "hw/net/xlnx-versal-canfd.h" 35 36 #define TYPE_XLNX_VERSAL "xlnx-versal" 37 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 38 39 #define XLNX_VERSAL_NR_ACPUS 2 40 #define XLNX_VERSAL_NR_RCPUS 2 41 #define XLNX_VERSAL_NR_UARTS 2 42 #define XLNX_VERSAL_NR_GEMS 2 43 #define XLNX_VERSAL_NR_ADMAS 8 44 #define XLNX_VERSAL_NR_SDS 2 45 #define XLNX_VERSAL_NR_XRAM 4 46 #define XLNX_VERSAL_NR_IRQS 192 47 #define XLNX_VERSAL_NR_CANFD 2 48 #define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000) 49 50 struct Versal { 51 /*< private >*/ 52 SysBusDevice parent_obj; 53 54 /*< public >*/ 55 struct { 56 struct { 57 MemoryRegion mr; 58 CPUClusterState cluster; 59 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 60 GICv3State gic; 61 } apu; 62 } fpd; 63 64 MemoryRegion mr_ps; 65 66 struct { 67 /* 4 ranges to access DDR. */ 68 MemoryRegion mr_ddr_ranges[4]; 69 } noc; 70 71 struct { 72 MemoryRegion mr_ocm; 73 74 struct { 75 PL011State uart[XLNX_VERSAL_NR_UARTS]; 76 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 77 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 78 VersalUsb2 usb; 79 CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 80 XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD]; 81 } iou; 82 83 /* Real-time Processing Unit. */ 84 struct { 85 MemoryRegion mr; 86 MemoryRegion mr_ps_alias; 87 88 CPUClusterState cluster; 89 ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; 90 } rpu; 91 92 struct { 93 OrIRQState irq_orgate; 94 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 95 } xram; 96 97 XlnxVersalCRL crl; 98 } lpd; 99 100 /* The Platform Management Controller subsystem. */ 101 struct { 102 struct { 103 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 104 XlnxVersalPmcIouSlcr slcr; 105 106 struct { 107 XlnxVersalOspi ospi; 108 XlnxCSUDMA dma_src; 109 XlnxCSUDMA dma_dst; 110 MemoryRegion linear_mr; 111 OrIRQState irq_orgate; 112 } ospi; 113 } iou; 114 115 XlnxZynqMPRTC rtc; 116 XlnxBBRam bbram; 117 XlnxEFuse efuse; 118 XlnxVersalEFuseCtrl efuse_ctrl; 119 XlnxVersalEFuseCache efuse_cache; 120 121 OrIRQState apb_irq_orgate; 122 } pmc; 123 124 struct { 125 MemoryRegion *mr_ddr; 126 } cfg; 127 }; 128 129 /* Memory-map and IRQ definitions. Copied a subset from 130 * auto-generated files. */ 131 132 #define VERSAL_GIC_MAINT_IRQ 9 133 #define VERSAL_TIMER_VIRT_IRQ 11 134 #define VERSAL_TIMER_S_EL1_IRQ 13 135 #define VERSAL_TIMER_NS_EL1_IRQ 14 136 #define VERSAL_TIMER_NS_EL2_IRQ 10 137 138 #define VERSAL_CRL_IRQ 10 139 #define VERSAL_UART0_IRQ_0 18 140 #define VERSAL_UART1_IRQ_0 19 141 #define VERSAL_CANFD0_IRQ_0 20 142 #define VERSAL_CANFD1_IRQ_0 21 143 #define VERSAL_USB0_IRQ_0 22 144 #define VERSAL_GEM0_IRQ_0 56 145 #define VERSAL_GEM0_WAKE_IRQ_0 57 146 #define VERSAL_GEM1_IRQ_0 58 147 #define VERSAL_GEM1_WAKE_IRQ_0 59 148 #define VERSAL_ADMA_IRQ_0 60 149 #define VERSAL_XRAM_IRQ_0 79 150 #define VERSAL_PMC_APB_IRQ 121 151 #define VERSAL_OSPI_IRQ 124 152 #define VERSAL_SD0_IRQ_0 126 153 #define VERSAL_EFUSE_IRQ 139 154 #define VERSAL_RTC_ALARM_IRQ 142 155 #define VERSAL_RTC_SECONDS_IRQ 143 156 157 /* Architecturally reserved IRQs suitable for virtualization. */ 158 #define VERSAL_RSVD_IRQ_FIRST 111 159 #define VERSAL_RSVD_IRQ_LAST 118 160 161 #define MM_TOP_RSVD 0xa0000000U 162 #define MM_TOP_RSVD_SIZE 0x4000000 163 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 164 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 165 #define MM_GIC_APU_REDIST_0 0xf9080000U 166 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 167 168 #define MM_UART0 0xff000000U 169 #define MM_UART0_SIZE 0x10000 170 #define MM_UART1 0xff010000U 171 #define MM_UART1_SIZE 0x10000 172 173 #define MM_CANFD0 0xff060000U 174 #define MM_CANFD0_SIZE 0x10000 175 #define MM_CANFD1 0xff070000U 176 #define MM_CANFD1_SIZE 0x10000 177 178 #define MM_GEM0 0xff0c0000U 179 #define MM_GEM0_SIZE 0x10000 180 #define MM_GEM1 0xff0d0000U 181 #define MM_GEM1_SIZE 0x10000 182 183 #define MM_ADMA_CH0 0xffa80000U 184 #define MM_ADMA_CH0_SIZE 0x10000 185 186 #define MM_OCM 0xfffc0000U 187 #define MM_OCM_SIZE 0x40000 188 189 #define MM_XRAM 0xfe800000 190 #define MM_XRAMC 0xff8e0000 191 #define MM_XRAMC_SIZE 0x10000 192 193 #define MM_USB2_CTRL_REGS 0xFF9D0000 194 #define MM_USB2_CTRL_REGS_SIZE 0x10000 195 196 #define MM_USB_0 0xFE200000 197 #define MM_USB_0_SIZE 0x10000 198 199 #define MM_TOP_DDR 0x0 200 #define MM_TOP_DDR_SIZE 0x80000000U 201 #define MM_TOP_DDR_2 0x800000000ULL 202 #define MM_TOP_DDR_2_SIZE 0x800000000ULL 203 #define MM_TOP_DDR_3 0xc000000000ULL 204 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 205 #define MM_TOP_DDR_4 0x10000000000ULL 206 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 207 208 #define MM_PSM_START 0xffc80000U 209 #define MM_PSM_END 0xffcf0000U 210 211 #define MM_CRL 0xff5e0000U 212 #define MM_CRL_SIZE 0x300000 213 #define MM_IOU_SCNTR 0xff130000U 214 #define MM_IOU_SCNTR_SIZE 0x10000 215 #define MM_IOU_SCNTRS 0xff140000U 216 #define MM_IOU_SCNTRS_SIZE 0x10000 217 #define MM_FPD_CRF 0xfd1a0000U 218 #define MM_FPD_CRF_SIZE 0x140000 219 #define MM_FPD_FPD_APU 0xfd5c0000 220 #define MM_FPD_FPD_APU_SIZE 0x100 221 222 #define MM_PMC_PMC_IOU_SLCR 0xf1060000 223 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 224 225 #define MM_PMC_OSPI 0xf1010000 226 #define MM_PMC_OSPI_SIZE 0x10000 227 228 #define MM_PMC_OSPI_DAC 0xc0000000 229 #define MM_PMC_OSPI_DAC_SIZE 0x20000000 230 231 #define MM_PMC_OSPI_DMA_DST 0xf1011800 232 #define MM_PMC_OSPI_DMA_SRC 0xf1011000 233 234 #define MM_PMC_SD0 0xf1040000U 235 #define MM_PMC_SD0_SIZE 0x10000 236 #define MM_PMC_BBRAM_CTRL 0xf11f0000 237 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 238 #define MM_PMC_EFUSE_CTRL 0xf1240000 239 #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 240 #define MM_PMC_EFUSE_CACHE 0xf1250000 241 #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 242 243 #define MM_PMC_CRP 0xf1260000U 244 #define MM_PMC_CRP_SIZE 0x10000 245 #define MM_PMC_RTC 0xf12a0000 246 #define MM_PMC_RTC_SIZE 0x10000 247 #endif 248