xref: /openbmc/qemu/include/hw/arm/stm32l4x5_soc.h (revision 34cc54fb)
1 /*
2  * STM32L4x5 SoC family
3  *
4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * This work is heavily inspired by the stm32f405_soc by Alistair Francis.
13  * Original code is licensed under the MIT License:
14  *
15  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
16  */
17 
18 /*
19  * The reference used is the STMicroElectronics RM0351 Reference manual
20  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
22  */
23 
24 #ifndef HW_ARM_STM32L4x5_SOC_H
25 #define HW_ARM_STM32L4x5_SOC_H
26 
27 #include "exec/memory.h"
28 #include "hw/arm/armv7m.h"
29 #include "hw/or-irq.h"
30 #include "hw/misc/stm32l4x5_syscfg.h"
31 #include "hw/misc/stm32l4x5_exti.h"
32 #include "hw/misc/stm32l4x5_rcc.h"
33 #include "hw/gpio/stm32l4x5_gpio.h"
34 #include "hw/char/stm32l4x5_usart.h"
35 #include "qom/object.h"
36 
37 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
38 #define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc"
39 #define TYPE_STM32L4X5XE_SOC "stm32l4x5xe-soc"
40 #define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc"
41 OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
42 
43 #define NUM_EXTI_OR_GATES 4
44 
45 #define STM_NUM_USARTS 3
46 #define STM_NUM_UARTS 2
47 
48 struct Stm32l4x5SocState {
49     SysBusDevice parent_obj;
50 
51     ARMv7MState armv7m;
52 
53     Stm32l4x5ExtiState exti;
54     OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
55     Stm32l4x5SyscfgState syscfg;
56     Stm32l4x5RccState rcc;
57     Stm32l4x5GpioState gpio[NUM_GPIOS];
58     Stm32l4x5UsartBaseState usart[STM_NUM_USARTS];
59     Stm32l4x5UsartBaseState uart[STM_NUM_UARTS];
60     Stm32l4x5UsartBaseState lpuart;
61 
62     MemoryRegion sram1;
63     MemoryRegion sram2;
64     MemoryRegion flash;
65     MemoryRegion flash_alias;
66 };
67 
68 struct Stm32l4x5SocClass {
69     SysBusDeviceClass parent_class;
70 
71     size_t flash_size;
72 };
73 
74 #endif
75