1 /* 2 * STM32F205 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef HW_ARM_STM32F205_SOC_H 26 #define HW_ARM_STM32F205_SOC_H 27 28 #include "hw/misc/stm32f2xx_syscfg.h" 29 #include "hw/timer/stm32f2xx_timer.h" 30 #include "hw/char/stm32f2xx_usart.h" 31 #include "hw/adc/stm32f2xx_adc.h" 32 #include "hw/or-irq.h" 33 #include "hw/ssi/stm32f2xx_spi.h" 34 #include "hw/arm/armv7m.h" 35 #include "qom/object.h" 36 37 #define TYPE_STM32F205_SOC "stm32f205-soc" 38 OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC) 39 40 #define STM_NUM_USARTS 6 41 #define STM_NUM_TIMERS 4 42 #define STM_NUM_ADCS 3 43 #define STM_NUM_SPIS 3 44 45 #define FLASH_BASE_ADDRESS 0x08000000 46 #define FLASH_SIZE (1024 * 1024) 47 #define SRAM_BASE_ADDRESS 0x20000000 48 #define SRAM_SIZE (128 * 1024) 49 50 struct STM32F205State { 51 /*< private >*/ 52 SysBusDevice parent_obj; 53 /*< public >*/ 54 55 char *cpu_type; 56 57 ARMv7MState armv7m; 58 59 STM32F2XXSyscfgState syscfg; 60 STM32F2XXUsartState usart[STM_NUM_USARTS]; 61 STM32F2XXTimerState timer[STM_NUM_TIMERS]; 62 STM32F2XXADCState adc[STM_NUM_ADCS]; 63 STM32F2XXSPIState spi[STM_NUM_SPIS]; 64 65 qemu_or_irq *adc_irqs; 66 }; 67 68 #endif 69