xref: /openbmc/qemu/include/hw/arm/smmuv3.h (revision ffe98631)
1 /*
2  * Copyright (C) 2014-2016 Broadcom Corporation
3  * Copyright (c) 2017 Red Hat, Inc.
4  * Written by Prem Mallappa, Eric Auger
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #ifndef HW_ARM_SMMUV3_H
20 #define HW_ARM_SMMUV3_H
21 
22 #include "hw/arm/smmu-common.h"
23 #include "hw/registerfields.h"
24 #include "qom/object.h"
25 
26 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
27 
28 typedef struct SMMUQueue {
29      uint64_t base; /* base register */
30      uint32_t prod;
31      uint32_t cons;
32      uint8_t entry_size;
33      uint8_t log2size;
34 } SMMUQueue;
35 
36 struct SMMUv3State {
37     SMMUState     smmu_state;
38 
39     uint32_t features;
40     uint8_t sid_size;
41     uint8_t sid_split;
42 
43     uint32_t idr[6];
44     uint32_t iidr;
45     uint32_t aidr;
46     uint32_t cr[3];
47     uint32_t cr0ack;
48     uint32_t statusr;
49     uint32_t irq_ctrl;
50     uint32_t gerror;
51     uint32_t gerrorn;
52     uint64_t gerror_irq_cfg0;
53     uint32_t gerror_irq_cfg1;
54     uint32_t gerror_irq_cfg2;
55     uint64_t strtab_base;
56     uint32_t strtab_base_cfg;
57     uint64_t eventq_irq_cfg0;
58     uint32_t eventq_irq_cfg1;
59     uint32_t eventq_irq_cfg2;
60 
61     SMMUQueue eventq, cmdq;
62 
63     qemu_irq     irq[4];
64     QemuMutex mutex;
65 };
66 
67 typedef enum {
68     SMMU_IRQ_EVTQ,
69     SMMU_IRQ_PRIQ,
70     SMMU_IRQ_CMD_SYNC,
71     SMMU_IRQ_GERROR,
72 } SMMUIrq;
73 
74 struct SMMUv3Class {
75     /*< private >*/
76     SMMUBaseClass smmu_base_class;
77     /*< public >*/
78 
79     DeviceRealize parent_realize;
80     ResettablePhases parent_phases;
81 };
82 
83 #define TYPE_ARM_SMMUV3   "arm-smmuv3"
84 OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
85 
86 #endif
87