1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 #include "qom/object.h" 25 26 #define SMMU_PCI_BUS_MAX 256 27 #define SMMU_PCI_DEVFN_MAX 256 28 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 29 30 /* VMSAv8-64 Translation constants and functions */ 31 #define VMSA_LEVELS 4 32 #define VMSA_MAX_S2_CONCAT 16 33 34 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) 35 #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ 36 (VMSA_LEVELS - (lvl))) 37 #define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ 38 VMSA_BIT_LVL(isz, strd, lvl)) - 1) 39 40 /* 41 * Page table walk error types 42 */ 43 typedef enum { 44 SMMU_PTW_ERR_NONE, 45 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 46 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 47 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 48 SMMU_PTW_ERR_ACCESS, /* Access fault */ 49 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 50 } SMMUPTWEventType; 51 52 typedef struct SMMUPTWEventInfo { 53 int stage; 54 SMMUPTWEventType type; 55 dma_addr_t addr; /* fetched address that induced an abort, if any */ 56 } SMMUPTWEventInfo; 57 58 typedef struct SMMUTransTableInfo { 59 bool disabled; /* is the translation table disabled? */ 60 uint64_t ttb; /* TT base address */ 61 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 62 uint8_t granule_sz; /* granule page shift */ 63 bool had; /* hierarchical attribute disable */ 64 } SMMUTransTableInfo; 65 66 typedef struct SMMUTLBEntry { 67 IOMMUTLBEntry entry; 68 uint8_t level; 69 uint8_t granule; 70 } SMMUTLBEntry; 71 72 /* Stage-2 configuration. */ 73 typedef struct SMMUS2Cfg { 74 uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ 75 uint8_t sl0; /* Start level of translation (S2SL0) */ 76 bool affd; /* AF Fault Disable (S2AFFD) */ 77 bool record_faults; /* Record fault events (S2R) */ 78 uint8_t granule_sz; /* Granule page shift (based on S2TG) */ 79 uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ 80 uint16_t vmid; /* Virtual Machine ID (S2VMID) */ 81 uint64_t vttb; /* Address of translation table base (S2TTB) */ 82 } SMMUS2Cfg; 83 84 /* 85 * Generic structure populated by derived SMMU devices 86 * after decoding the configuration information and used as 87 * input to the page table walk 88 */ 89 typedef struct SMMUTransCfg { 90 /* Shared fields between stage-1 and stage-2. */ 91 int stage; /* translation stage */ 92 bool disabled; /* smmu is disabled */ 93 bool bypassed; /* translation is bypassed */ 94 bool aborted; /* translation is aborted */ 95 uint32_t iotlb_hits; /* counts IOTLB hits */ 96 uint32_t iotlb_misses; /* counts IOTLB misses*/ 97 /* Used by stage-1 only. */ 98 bool aa64; /* arch64 or aarch32 translation table */ 99 bool record_faults; /* record fault events */ 100 uint64_t ttb; /* TT base address */ 101 uint8_t oas; /* output address width */ 102 uint8_t tbi; /* Top Byte Ignore */ 103 uint16_t asid; 104 SMMUTransTableInfo tt[2]; 105 /* Used by stage-2 only. */ 106 struct SMMUS2Cfg s2cfg; 107 } SMMUTransCfg; 108 109 typedef struct SMMUDevice { 110 void *smmu; 111 PCIBus *bus; 112 int devfn; 113 IOMMUMemoryRegion iommu; 114 AddressSpace as; 115 uint32_t cfg_cache_hits; 116 uint32_t cfg_cache_misses; 117 QLIST_ENTRY(SMMUDevice) next; 118 } SMMUDevice; 119 120 typedef struct SMMUPciBus { 121 PCIBus *bus; 122 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 123 } SMMUPciBus; 124 125 typedef struct SMMUIOTLBKey { 126 uint64_t iova; 127 uint16_t asid; 128 uint16_t vmid; 129 uint8_t tg; 130 uint8_t level; 131 } SMMUIOTLBKey; 132 133 struct SMMUState { 134 /* <private> */ 135 SysBusDevice dev; 136 const char *mrtypename; 137 MemoryRegion iomem; 138 139 GHashTable *smmu_pcibus_by_busptr; 140 GHashTable *configs; /* cache for configuration data */ 141 GHashTable *iotlb; 142 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 143 PCIBus *pci_bus; 144 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 145 uint8_t bus_num; 146 PCIBus *primary_bus; 147 }; 148 149 struct SMMUBaseClass { 150 /* <private> */ 151 SysBusDeviceClass parent_class; 152 153 /*< public >*/ 154 155 DeviceRealize parent_realize; 156 157 }; 158 159 #define TYPE_ARM_SMMU "arm-smmu" 160 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) 161 162 /* Return the SMMUPciBus handle associated to a PCI bus number */ 163 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 164 165 /* Return the stream ID of an SMMU device */ 166 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 167 { 168 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 169 } 170 171 /** 172 * smmu_ptw - Perform the page table walk for a given iova / access flags 173 * pair, according to @cfg translation config 174 */ 175 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 176 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 177 178 /** 179 * select_tt - compute which translation table shall be used according to 180 * the input iova and translation config and return the TT specific info 181 */ 182 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 183 184 /* Return the iommu mr associated to @sid, or NULL if none */ 185 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); 186 187 #define SMMU_IOTLB_MAX_SIZE 256 188 189 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 190 SMMUTransTableInfo *tt, hwaddr iova); 191 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 192 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, 193 uint8_t tg, uint8_t level); 194 void smmu_iotlb_inv_all(SMMUState *s); 195 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); 196 void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); 197 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, 198 uint8_t tg, uint64_t num_pages, uint8_t ttl); 199 200 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 201 void smmu_inv_notifiers_all(SMMUState *s); 202 203 #endif /* HW_ARM_SMMU_COMMON_H */ 204