1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 #include "qom/object.h" 25 26 #define SMMU_PCI_BUS_MAX 256 27 #define SMMU_PCI_DEVFN_MAX 256 28 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 29 30 /* VMSAv8-64 Translation constants and functions */ 31 #define VMSA_LEVELS 4 32 #define VMSA_MAX_S2_CONCAT 16 33 34 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) 35 #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ 36 (VMSA_LEVELS - (lvl))) 37 #define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ 38 VMSA_BIT_LVL(isz, strd, lvl)) - 1) 39 40 /* 41 * Page table walk error types 42 */ 43 typedef enum { 44 SMMU_PTW_ERR_NONE, 45 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 46 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 47 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 48 SMMU_PTW_ERR_ACCESS, /* Access fault */ 49 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 50 } SMMUPTWEventType; 51 52 typedef struct SMMUPTWEventInfo { 53 int stage; 54 SMMUPTWEventType type; 55 dma_addr_t addr; /* fetched address that induced an abort, if any */ 56 } SMMUPTWEventInfo; 57 58 typedef struct SMMUTransTableInfo { 59 bool disabled; /* is the translation table disabled? */ 60 uint64_t ttb; /* TT base address */ 61 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 62 uint8_t granule_sz; /* granule page shift */ 63 bool had; /* hierarchical attribute disable */ 64 } SMMUTransTableInfo; 65 66 typedef struct SMMUTLBEntry { 67 IOMMUTLBEntry entry; 68 uint8_t level; 69 uint8_t granule; 70 } SMMUTLBEntry; 71 72 /* Stage-2 configuration. */ 73 typedef struct SMMUS2Cfg { 74 uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ 75 uint8_t sl0; /* Start level of translation (S2SL0) */ 76 bool affd; /* AF Fault Disable (S2AFFD) */ 77 bool record_faults; /* Record fault events (S2R) */ 78 uint8_t granule_sz; /* Granule page shift (based on S2TG) */ 79 uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ 80 uint16_t vmid; /* Virtual Machine ID (S2VMID) */ 81 uint64_t vttb; /* Address of translation table base (S2TTB) */ 82 } SMMUS2Cfg; 83 84 /* 85 * Generic structure populated by derived SMMU devices 86 * after decoding the configuration information and used as 87 * input to the page table walk 88 */ 89 typedef struct SMMUTransCfg { 90 /* Shared fields between stage-1 and stage-2. */ 91 int stage; /* translation stage */ 92 bool disabled; /* smmu is disabled */ 93 bool bypassed; /* translation is bypassed */ 94 bool aborted; /* translation is aborted */ 95 bool affd; /* AF fault disable */ 96 uint32_t iotlb_hits; /* counts IOTLB hits */ 97 uint32_t iotlb_misses; /* counts IOTLB misses*/ 98 /* Used by stage-1 only. */ 99 bool aa64; /* arch64 or aarch32 translation table */ 100 bool record_faults; /* record fault events */ 101 uint64_t ttb; /* TT base address */ 102 uint8_t oas; /* output address width */ 103 uint8_t tbi; /* Top Byte Ignore */ 104 uint16_t asid; 105 SMMUTransTableInfo tt[2]; 106 /* Used by stage-2 only. */ 107 struct SMMUS2Cfg s2cfg; 108 } SMMUTransCfg; 109 110 typedef struct SMMUDevice { 111 void *smmu; 112 PCIBus *bus; 113 int devfn; 114 IOMMUMemoryRegion iommu; 115 AddressSpace as; 116 uint32_t cfg_cache_hits; 117 uint32_t cfg_cache_misses; 118 QLIST_ENTRY(SMMUDevice) next; 119 } SMMUDevice; 120 121 typedef struct SMMUPciBus { 122 PCIBus *bus; 123 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 124 } SMMUPciBus; 125 126 typedef struct SMMUIOTLBKey { 127 uint64_t iova; 128 uint16_t asid; 129 uint16_t vmid; 130 uint8_t tg; 131 uint8_t level; 132 } SMMUIOTLBKey; 133 134 struct SMMUState { 135 /* <private> */ 136 SysBusDevice dev; 137 const char *mrtypename; 138 MemoryRegion iomem; 139 140 GHashTable *smmu_pcibus_by_busptr; 141 GHashTable *configs; /* cache for configuration data */ 142 GHashTable *iotlb; 143 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 144 PCIBus *pci_bus; 145 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 146 uint8_t bus_num; 147 PCIBus *primary_bus; 148 }; 149 150 struct SMMUBaseClass { 151 /* <private> */ 152 SysBusDeviceClass parent_class; 153 154 /*< public >*/ 155 156 DeviceRealize parent_realize; 157 158 }; 159 160 #define TYPE_ARM_SMMU "arm-smmu" 161 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) 162 163 /* Return the SMMUPciBus handle associated to a PCI bus number */ 164 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 165 166 /* Return the stream ID of an SMMU device */ 167 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 168 { 169 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 170 } 171 172 /** 173 * smmu_ptw - Perform the page table walk for a given iova / access flags 174 * pair, according to @cfg translation config 175 */ 176 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 177 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 178 179 /** 180 * select_tt - compute which translation table shall be used according to 181 * the input iova and translation config and return the TT specific info 182 */ 183 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 184 185 /* Return the iommu mr associated to @sid, or NULL if none */ 186 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); 187 188 #define SMMU_IOTLB_MAX_SIZE 256 189 190 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 191 SMMUTransTableInfo *tt, hwaddr iova); 192 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 193 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, 194 uint8_t tg, uint8_t level); 195 void smmu_iotlb_inv_all(SMMUState *s); 196 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); 197 void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); 198 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, 199 uint8_t tg, uint64_t num_pages, uint8_t ttl); 200 201 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 202 void smmu_inv_notifiers_all(SMMUState *s); 203 204 #endif /* HW_ARM_SMMU_COMMON_H */ 205