1 /* 2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines 3 * 4 * These definitions are derived from those in Raspbian Linux at 5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h 6 * where they carry the following notice: 7 * 8 * Copyright (C) 2010 Broadcom 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program. If not, see <https://www.gnu.org/licenses/>. 22 * 23 * Various undocumented addresses and names come from Herman Hermitage's VC4 24 * documentation: 25 * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map 26 */ 27 28 #ifndef HW_ARM_RASPI_PLATFORM_H 29 #define HW_ARM_RASPI_PLATFORM_H 30 31 #include "hw/boards.h" 32 #include "hw/arm/boot.h" 33 34 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 35 #define MACH_TYPE_BCM2708 3138 36 37 #define TYPE_RASPI_BASE_MACHINE MACHINE_TYPE_NAME("raspi-base") 38 OBJECT_DECLARE_TYPE(RaspiBaseMachineState, RaspiBaseMachineClass, 39 RASPI_BASE_MACHINE) 40 41 struct RaspiBaseMachineState { 42 /*< private >*/ 43 MachineState parent_obj; 44 /*< public >*/ 45 struct arm_boot_info binfo; 46 }; 47 48 struct RaspiBaseMachineClass { 49 /*< private >*/ 50 MachineClass parent_obj; 51 /*< public >*/ 52 uint32_t board_rev; 53 }; 54 55 /* Common functions for raspberry pi machines */ 56 const char *board_soc_type(uint32_t board_rev); 57 void raspi_machine_init(MachineState *machine); 58 59 typedef struct BCM283XBaseState BCM283XBaseState; 60 void raspi_base_machine_init(MachineState *machine, 61 BCM283XBaseState *soc); 62 63 void raspi_machine_class_common_init(MachineClass *mc, 64 uint32_t board_rev); 65 uint64_t board_ram_size(uint32_t board_rev); 66 67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ 68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ 69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */ 70 #define ST_OFFSET 0x3000 /* System Timer */ 71 #define TXP_OFFSET 0x4000 /* Transposer */ 72 #define JPEG_OFFSET 0x5000 73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ 74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ 75 #define ARBA_OFFSET 0x9000 76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */ 77 #define ARM_OFFSET 0xB000 /* ARM control block */ 78 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) 79 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ 80 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ 81 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores 82 * Doorbells & Mailboxes */ 83 #define PM_OFFSET 0x100000 /* Power Management */ 84 #define CPRMAN_OFFSET 0x101000 /* Clock Management */ 85 #define AVS_OFFSET 0x103000 /* Audio Video Standard */ 86 #define RNG_OFFSET 0x104000 87 #define GPIO_OFFSET 0x200000 88 #define UART0_OFFSET 0x201000 /* PL011 */ 89 #define MMCI0_OFFSET 0x202000 /* Legacy MMC */ 90 #define I2S_OFFSET 0x203000 /* PCM */ 91 #define SPI0_OFFSET 0x204000 /* SPI master */ 92 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ 93 #define PIXV0_OFFSET 0x206000 94 #define PIXV1_OFFSET 0x207000 95 #define DPI_OFFSET 0x208000 96 #define DSI0_OFFSET 0x209000 /* Display Serial Interface */ 97 #define PWM_OFFSET 0x20c000 98 #define PERM_OFFSET 0x20d000 99 #define TEC_OFFSET 0x20e000 100 #define OTP_OFFSET 0x20f000 101 #define SLIM_OFFSET 0x210000 /* SLIMbus */ 102 #define CPG_OFFSET 0x211000 103 #define THERMAL_OFFSET 0x212000 104 #define AVSP_OFFSET 0x213000 105 #define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ 106 #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ 107 #define EMMC1_OFFSET 0x300000 108 #define EMMC2_OFFSET 0x340000 109 #define HVS_OFFSET 0x400000 110 #define SMI_OFFSET 0x600000 111 #define DSI1_OFFSET 0x700000 112 #define UCAM_OFFSET 0x800000 113 #define CMI_OFFSET 0x802000 114 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ 115 #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ 116 #define VECA_OFFSET 0x806000 117 #define PIXV2_OFFSET 0x807000 118 #define HDMI_OFFSET 0x808000 119 #define HDCP_OFFSET 0x809000 120 #define ARBR0_OFFSET 0x80a000 121 #define DBUS_OFFSET 0x900000 122 #define AVE0_OFFSET 0x910000 123 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ 124 #define V3D_OFFSET 0xc00000 125 #define SDRAMC_OFFSET 0xe00000 126 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ 127 #define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ 128 #define ARBR1_OFFSET 0xe04000 129 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ 130 #define DCRC_OFFSET 0xe07000 131 #define AXIP_OFFSET 0xe08000 132 133 /* GPU interrupts */ 134 #define INTERRUPT_TIMER0 0 135 #define INTERRUPT_TIMER1 1 136 #define INTERRUPT_TIMER2 2 137 #define INTERRUPT_TIMER3 3 138 #define INTERRUPT_CODEC0 4 139 #define INTERRUPT_CODEC1 5 140 #define INTERRUPT_CODEC2 6 141 #define INTERRUPT_JPEG 7 142 #define INTERRUPT_ISP 8 143 #define INTERRUPT_USB 9 144 #define INTERRUPT_3D 10 145 #define INTERRUPT_TRANSPOSER 11 146 #define INTERRUPT_MULTICORESYNC0 12 147 #define INTERRUPT_MULTICORESYNC1 13 148 #define INTERRUPT_MULTICORESYNC2 14 149 #define INTERRUPT_MULTICORESYNC3 15 150 #define INTERRUPT_DMA0 16 151 #define INTERRUPT_DMA1 17 152 #define INTERRUPT_DMA2 18 153 #define INTERRUPT_DMA3 19 154 #define INTERRUPT_DMA4 20 155 #define INTERRUPT_DMA5 21 156 #define INTERRUPT_DMA6 22 157 #define INTERRUPT_DMA7 23 158 #define INTERRUPT_DMA8 24 159 #define INTERRUPT_DMA9 25 160 #define INTERRUPT_DMA10 26 161 #define INTERRUPT_DMA11 27 162 #define INTERRUPT_DMA12 28 163 #define INTERRUPT_AUX 29 164 #define INTERRUPT_ARM 30 165 #define INTERRUPT_VPUDMA 31 166 #define INTERRUPT_HOSTPORT 32 167 #define INTERRUPT_VIDEOSCALER 33 168 #define INTERRUPT_CCP2TX 34 169 #define INTERRUPT_SDC 35 170 #define INTERRUPT_DSI0 36 171 #define INTERRUPT_AVE 37 172 #define INTERRUPT_CAM0 38 173 #define INTERRUPT_CAM1 39 174 #define INTERRUPT_HDMI0 40 175 #define INTERRUPT_HDMI1 41 176 #define INTERRUPT_PIXELVALVE1 42 177 #define INTERRUPT_I2CSPISLV 43 178 #define INTERRUPT_DSI1 44 179 #define INTERRUPT_PWA0 45 180 #define INTERRUPT_PWA1 46 181 #define INTERRUPT_CPR 47 182 #define INTERRUPT_SMI 48 183 #define INTERRUPT_GPIO0 49 184 #define INTERRUPT_GPIO1 50 185 #define INTERRUPT_GPIO2 51 186 #define INTERRUPT_GPIO3 52 187 #define INTERRUPT_I2C 53 188 #define INTERRUPT_SPI 54 189 #define INTERRUPT_I2SPCM 55 190 #define INTERRUPT_SDIO 56 191 #define INTERRUPT_UART0 57 192 #define INTERRUPT_SLIMBUS 58 193 #define INTERRUPT_VEC 59 194 #define INTERRUPT_CPG 60 195 #define INTERRUPT_RNG 61 196 #define INTERRUPT_ARASANSDIO 62 197 #define INTERRUPT_AVSPMON 63 198 199 /* ARM CPU IRQs use a private number space */ 200 #define INTERRUPT_ARM_TIMER 0 201 #define INTERRUPT_ARM_MAILBOX 1 202 #define INTERRUPT_ARM_DOORBELL_0 2 203 #define INTERRUPT_ARM_DOORBELL_1 3 204 #define INTERRUPT_VPU0_HALTED 4 205 #define INTERRUPT_VPU1_HALTED 5 206 #define INTERRUPT_ILLEGAL_TYPE0 6 207 #define INTERRUPT_ILLEGAL_TYPE1 7 208 209 /* Clock rates */ 210 #define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 211 #define RPI_FIRMWARE_UART_CLK_RATE 3000000 212 /* 213 * TODO: this is really SoC-specific; we might want to 214 * set it per-SoC if it turns out any guests care. 215 */ 216 #define RPI_FIRMWARE_CORE_CLK_RATE 350000000 217 #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 218 219 #endif 220