1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "hw/input/tsc2xxx.h" 25 #include "target/arm/cpu-qom.h" 26 #include "qemu/log.h" 27 #include "qom/object.h" 28 29 # define OMAP_EMIFS_BASE 0x00000000 30 # define OMAP2_Q0_BASE 0x00000000 31 # define OMAP_CS0_BASE 0x00000000 32 # define OMAP_CS1_BASE 0x04000000 33 # define OMAP_CS2_BASE 0x08000000 34 # define OMAP_CS3_BASE 0x0c000000 35 # define OMAP_EMIFF_BASE 0x10000000 36 # define OMAP_IMIF_BASE 0x20000000 37 # define OMAP_LOCALBUS_BASE 0x30000000 38 # define OMAP2_Q1_BASE 0x40000000 39 # define OMAP2_L4_BASE 0x48000000 40 # define OMAP2_SRAM_BASE 0x40200000 41 # define OMAP2_L3_BASE 0x68000000 42 # define OMAP2_Q2_BASE 0x80000000 43 # define OMAP2_Q3_BASE 0xc0000000 44 # define OMAP_MPUI_BASE 0xe1000000 45 46 # define OMAP730_SRAM_SIZE 0x00032000 47 # define OMAP15XX_SRAM_SIZE 0x00030000 48 # define OMAP16XX_SRAM_SIZE 0x00004000 49 # define OMAP1611_SRAM_SIZE 0x0003e800 50 # define OMAP242X_SRAM_SIZE 0x000a0000 51 # define OMAP243X_SRAM_SIZE 0x00010000 52 # define OMAP_CS0_SIZE 0x04000000 53 # define OMAP_CS1_SIZE 0x04000000 54 # define OMAP_CS2_SIZE 0x04000000 55 # define OMAP_CS3_SIZE 0x04000000 56 57 /* omap_clk.c */ 58 struct omap_mpu_state_s; 59 typedef struct clk *omap_clk; 60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 61 void omap_clk_init(struct omap_mpu_state_s *mpu); 62 void omap_clk_adduser(struct clk *clk, qemu_irq user); 63 void omap_clk_get(omap_clk clk); 64 void omap_clk_put(omap_clk clk); 65 void omap_clk_onoff(omap_clk clk, int on); 66 void omap_clk_canidle(omap_clk clk, int can); 67 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 68 int64_t omap_clk_getrate(omap_clk clk); 69 void omap_clk_reparent(omap_clk clk, omap_clk parent); 70 71 /* omap_intc.c */ 72 #define TYPE_OMAP_INTC "common-omap-intc" 73 typedef struct OMAPIntcState OMAPIntcState; 74 DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) 75 76 77 /* 78 * TODO: Ideally we should have a clock framework that 79 * let us wire these clocks up with QOM properties or links. 80 * 81 * qdev should support a generic means of defining a 'port' with 82 * an arbitrary interface for connecting two devices. Then we 83 * could reframe the omap clock API in terms of clock ports, 84 * and get some type safety. For now the best qdev provides is 85 * passing an arbitrary pointer. 86 * (It's not possible to pass in the string which is the clock 87 * name, because this device does not have the necessary information 88 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 89 * translation.) 90 */ 91 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); 92 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); 93 94 /* omap_i2c.c */ 95 #define TYPE_OMAP_I2C "omap_i2c" 96 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 97 98 99 /* TODO: clock framework (see above) */ 100 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 101 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 102 103 /* omap_gpio.c */ 104 #define TYPE_OMAP1_GPIO "omap-gpio" 105 typedef struct Omap1GpioState Omap1GpioState; 106 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 107 TYPE_OMAP1_GPIO) 108 109 #define TYPE_OMAP2_GPIO "omap2-gpio" 110 typedef struct Omap2GpioState Omap2GpioState; 111 DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO, 112 TYPE_OMAP2_GPIO) 113 114 /* TODO: clock framework (see above) */ 115 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 116 117 void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk); 118 void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk); 119 120 /* OMAP2 l4 Interconnect */ 121 struct omap_l4_s; 122 struct omap_l4_region_s { 123 hwaddr offset; 124 size_t size; 125 int access; 126 }; 127 struct omap_l4_agent_info_s { 128 int ta; 129 int region; 130 int regions; 131 int ta_region; 132 }; 133 struct omap_target_agent_s { 134 MemoryRegion iomem; 135 struct omap_l4_s *bus; 136 int regions; 137 const struct omap_l4_region_s *start; 138 hwaddr base; 139 uint32_t component; 140 uint32_t control; 141 uint32_t status; 142 }; 143 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 144 hwaddr base, int ta_num); 145 146 struct omap_target_agent_s; 147 struct omap_target_agent_s *omap_l4ta_get( 148 struct omap_l4_s *bus, 149 const struct omap_l4_region_s *regions, 150 const struct omap_l4_agent_info_s *agents, 151 int cs); 152 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 153 int region, MemoryRegion *mr); 154 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 155 int region); 156 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 157 int region); 158 159 /* OMAP2 SDRAM controller */ 160 struct omap_sdrc_s; 161 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 162 hwaddr base); 163 void omap_sdrc_reset(struct omap_sdrc_s *s); 164 165 /* OMAP2 general purpose memory controller */ 166 struct omap_gpmc_s; 167 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 168 hwaddr base, 169 qemu_irq irq, qemu_irq drq); 170 void omap_gpmc_reset(struct omap_gpmc_s *s); 171 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 172 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 173 174 /* 175 * Common IRQ numbers for level 1 interrupt handler 176 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 177 */ 178 # define OMAP_INT_CAMERA 1 179 # define OMAP_INT_FIQ 3 180 # define OMAP_INT_RTDX 6 181 # define OMAP_INT_DSP_MMU_ABORT 7 182 # define OMAP_INT_HOST 8 183 # define OMAP_INT_ABORT 9 184 # define OMAP_INT_BRIDGE_PRIV 13 185 # define OMAP_INT_GPIO_BANK1 14 186 # define OMAP_INT_UART3 15 187 # define OMAP_INT_TIMER3 16 188 # define OMAP_INT_DMA_CH0_6 19 189 # define OMAP_INT_DMA_CH1_7 20 190 # define OMAP_INT_DMA_CH2_8 21 191 # define OMAP_INT_DMA_CH3 22 192 # define OMAP_INT_DMA_CH4 23 193 # define OMAP_INT_DMA_CH5 24 194 # define OMAP_INT_DMA_LCD 25 195 # define OMAP_INT_TIMER1 26 196 # define OMAP_INT_WD_TIMER 27 197 # define OMAP_INT_BRIDGE_PUB 28 198 # define OMAP_INT_TIMER2 30 199 # define OMAP_INT_LCD_CTRL 31 200 201 /* 202 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 203 */ 204 # define OMAP_INT_15XX_IH2_IRQ 0 205 # define OMAP_INT_15XX_LB_MMU 17 206 # define OMAP_INT_15XX_LOCAL_BUS 29 207 208 /* 209 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 210 */ 211 # define OMAP_INT_1510_SPI_TX 4 212 # define OMAP_INT_1510_SPI_RX 5 213 # define OMAP_INT_1510_DSP_MAILBOX1 10 214 # define OMAP_INT_1510_DSP_MAILBOX2 11 215 216 /* 217 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 218 */ 219 # define OMAP_INT_310_McBSP2_TX 4 220 # define OMAP_INT_310_McBSP2_RX 5 221 # define OMAP_INT_310_HSB_MAILBOX1 12 222 # define OMAP_INT_310_HSAB_MMU 18 223 224 /* 225 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 226 */ 227 # define OMAP_INT_1610_IH2_IRQ 0 228 # define OMAP_INT_1610_IH2_FIQ 2 229 # define OMAP_INT_1610_McBSP2_TX 4 230 # define OMAP_INT_1610_McBSP2_RX 5 231 # define OMAP_INT_1610_DSP_MAILBOX1 10 232 # define OMAP_INT_1610_DSP_MAILBOX2 11 233 # define OMAP_INT_1610_LCD_LINE 12 234 # define OMAP_INT_1610_GPTIMER1 17 235 # define OMAP_INT_1610_GPTIMER2 18 236 # define OMAP_INT_1610_SSR_FIFO_0 29 237 238 /* 239 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 240 */ 241 # define OMAP_INT_730_IH2_FIQ 0 242 # define OMAP_INT_730_IH2_IRQ 1 243 # define OMAP_INT_730_USB_NON_ISO 2 244 # define OMAP_INT_730_USB_ISO 3 245 # define OMAP_INT_730_ICR 4 246 # define OMAP_INT_730_EAC 5 247 # define OMAP_INT_730_GPIO_BANK1 6 248 # define OMAP_INT_730_GPIO_BANK2 7 249 # define OMAP_INT_730_GPIO_BANK3 8 250 # define OMAP_INT_730_McBSP2TX 10 251 # define OMAP_INT_730_McBSP2RX 11 252 # define OMAP_INT_730_McBSP2RX_OVF 12 253 # define OMAP_INT_730_LCD_LINE 14 254 # define OMAP_INT_730_GSM_PROTECT 15 255 # define OMAP_INT_730_TIMER3 16 256 # define OMAP_INT_730_GPIO_BANK5 17 257 # define OMAP_INT_730_GPIO_BANK6 18 258 # define OMAP_INT_730_SPGIO_WR 29 259 260 /* 261 * Common IRQ numbers for level 2 interrupt handler 262 */ 263 # define OMAP_INT_KEYBOARD 1 264 # define OMAP_INT_uWireTX 2 265 # define OMAP_INT_uWireRX 3 266 # define OMAP_INT_I2C 4 267 # define OMAP_INT_MPUIO 5 268 # define OMAP_INT_USB_HHC_1 6 269 # define OMAP_INT_McBSP3TX 10 270 # define OMAP_INT_McBSP3RX 11 271 # define OMAP_INT_McBSP1TX 12 272 # define OMAP_INT_McBSP1RX 13 273 # define OMAP_INT_UART1 14 274 # define OMAP_INT_UART2 15 275 # define OMAP_INT_USB_W2FC 20 276 # define OMAP_INT_1WIRE 21 277 # define OMAP_INT_OS_TIMER 22 278 # define OMAP_INT_OQN 23 279 # define OMAP_INT_GAUGE_32K 24 280 # define OMAP_INT_RTC_TIMER 25 281 # define OMAP_INT_RTC_ALARM 26 282 # define OMAP_INT_DSP_MMU 28 283 284 /* 285 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 286 */ 287 # define OMAP_INT_1510_BT_MCSI1TX 16 288 # define OMAP_INT_1510_BT_MCSI1RX 17 289 # define OMAP_INT_1510_SoSSI_MATCH 19 290 # define OMAP_INT_1510_MEM_STICK 27 291 # define OMAP_INT_1510_COM_SPI_RO 31 292 293 /* 294 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 295 */ 296 # define OMAP_INT_310_FAC 0 297 # define OMAP_INT_310_USB_HHC_2 7 298 # define OMAP_INT_310_MCSI1_FE 16 299 # define OMAP_INT_310_MCSI2_FE 17 300 # define OMAP_INT_310_USB_W2FC_ISO 29 301 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 302 # define OMAP_INT_310_McBSP2RX_OF 31 303 304 /* 305 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 306 */ 307 # define OMAP_INT_1610_FAC 0 308 # define OMAP_INT_1610_USB_HHC_2 7 309 # define OMAP_INT_1610_USB_OTG 8 310 # define OMAP_INT_1610_SoSSI 9 311 # define OMAP_INT_1610_BT_MCSI1TX 16 312 # define OMAP_INT_1610_BT_MCSI1RX 17 313 # define OMAP_INT_1610_SoSSI_MATCH 19 314 # define OMAP_INT_1610_MEM_STICK 27 315 # define OMAP_INT_1610_McBSP2RX_OF 31 316 # define OMAP_INT_1610_STI 32 317 # define OMAP_INT_1610_STI_WAKEUP 33 318 # define OMAP_INT_1610_GPTIMER3 34 319 # define OMAP_INT_1610_GPTIMER4 35 320 # define OMAP_INT_1610_GPTIMER5 36 321 # define OMAP_INT_1610_GPTIMER6 37 322 # define OMAP_INT_1610_GPTIMER7 38 323 # define OMAP_INT_1610_GPTIMER8 39 324 # define OMAP_INT_1610_GPIO_BANK2 40 325 # define OMAP_INT_1610_GPIO_BANK3 41 326 # define OMAP_INT_1610_MMC2 42 327 # define OMAP_INT_1610_CF 43 328 # define OMAP_INT_1610_WAKE_UP_REQ 46 329 # define OMAP_INT_1610_GPIO_BANK4 48 330 # define OMAP_INT_1610_SPI 49 331 # define OMAP_INT_1610_DMA_CH6 53 332 # define OMAP_INT_1610_DMA_CH7 54 333 # define OMAP_INT_1610_DMA_CH8 55 334 # define OMAP_INT_1610_DMA_CH9 56 335 # define OMAP_INT_1610_DMA_CH10 57 336 # define OMAP_INT_1610_DMA_CH11 58 337 # define OMAP_INT_1610_DMA_CH12 59 338 # define OMAP_INT_1610_DMA_CH13 60 339 # define OMAP_INT_1610_DMA_CH14 61 340 # define OMAP_INT_1610_DMA_CH15 62 341 # define OMAP_INT_1610_NAND 63 342 343 /* 344 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 345 */ 346 # define OMAP_INT_730_HW_ERRORS 0 347 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 348 # define OMAP_INT_730_CFCD 2 349 # define OMAP_INT_730_CFIREQ 3 350 # define OMAP_INT_730_I2C 4 351 # define OMAP_INT_730_PCC 5 352 # define OMAP_INT_730_MPU_EXT_NIRQ 6 353 # define OMAP_INT_730_SPI_100K_1 7 354 # define OMAP_INT_730_SYREN_SPI 8 355 # define OMAP_INT_730_VLYNQ 9 356 # define OMAP_INT_730_GPIO_BANK4 10 357 # define OMAP_INT_730_McBSP1TX 11 358 # define OMAP_INT_730_McBSP1RX 12 359 # define OMAP_INT_730_McBSP1RX_OF 13 360 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 361 # define OMAP_INT_730_UART_MODEM_1 15 362 # define OMAP_INT_730_MCSI 16 363 # define OMAP_INT_730_uWireTX 17 364 # define OMAP_INT_730_uWireRX 18 365 # define OMAP_INT_730_SMC_CD 19 366 # define OMAP_INT_730_SMC_IREQ 20 367 # define OMAP_INT_730_HDQ_1WIRE 21 368 # define OMAP_INT_730_TIMER32K 22 369 # define OMAP_INT_730_MMC_SDIO 23 370 # define OMAP_INT_730_UPLD 24 371 # define OMAP_INT_730_USB_HHC_1 27 372 # define OMAP_INT_730_USB_HHC_2 28 373 # define OMAP_INT_730_USB_GENI 29 374 # define OMAP_INT_730_USB_OTG 30 375 # define OMAP_INT_730_CAMERA_IF 31 376 # define OMAP_INT_730_RNG 32 377 # define OMAP_INT_730_DUAL_MODE_TIMER 33 378 # define OMAP_INT_730_DBB_RF_EN 34 379 # define OMAP_INT_730_MPUIO_KEYPAD 35 380 # define OMAP_INT_730_SHA1_MD5 36 381 # define OMAP_INT_730_SPI_100K_2 37 382 # define OMAP_INT_730_RNG_IDLE 38 383 # define OMAP_INT_730_MPUIO 39 384 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 385 # define OMAP_INT_730_LLPC_OE_FALLING 41 386 # define OMAP_INT_730_LLPC_OE_RISING 42 387 # define OMAP_INT_730_LLPC_VSYNC 43 388 # define OMAP_INT_730_WAKE_UP_REQ 46 389 # define OMAP_INT_730_DMA_CH6 53 390 # define OMAP_INT_730_DMA_CH7 54 391 # define OMAP_INT_730_DMA_CH8 55 392 # define OMAP_INT_730_DMA_CH9 56 393 # define OMAP_INT_730_DMA_CH10 57 394 # define OMAP_INT_730_DMA_CH11 58 395 # define OMAP_INT_730_DMA_CH12 59 396 # define OMAP_INT_730_DMA_CH13 60 397 # define OMAP_INT_730_DMA_CH14 61 398 # define OMAP_INT_730_DMA_CH15 62 399 # define OMAP_INT_730_NAND 63 400 401 /* 402 * OMAP-24xx common IRQ numbers 403 */ 404 # define OMAP_INT_24XX_STI 4 405 # define OMAP_INT_24XX_SYS_NIRQ 7 406 # define OMAP_INT_24XX_L3_IRQ 10 407 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 408 # define OMAP_INT_24XX_SDMA_IRQ0 12 409 # define OMAP_INT_24XX_SDMA_IRQ1 13 410 # define OMAP_INT_24XX_SDMA_IRQ2 14 411 # define OMAP_INT_24XX_SDMA_IRQ3 15 412 # define OMAP_INT_243X_MCBSP2_IRQ 16 413 # define OMAP_INT_243X_MCBSP3_IRQ 17 414 # define OMAP_INT_243X_MCBSP4_IRQ 18 415 # define OMAP_INT_243X_MCBSP5_IRQ 19 416 # define OMAP_INT_24XX_GPMC_IRQ 20 417 # define OMAP_INT_24XX_GUFFAW_IRQ 21 418 # define OMAP_INT_24XX_IVA_IRQ 22 419 # define OMAP_INT_24XX_EAC_IRQ 23 420 # define OMAP_INT_24XX_CAM_IRQ 24 421 # define OMAP_INT_24XX_DSS_IRQ 25 422 # define OMAP_INT_24XX_MAIL_U0_MPU 26 423 # define OMAP_INT_24XX_DSP_UMA 27 424 # define OMAP_INT_24XX_DSP_MMU 28 425 # define OMAP_INT_24XX_GPIO_BANK1 29 426 # define OMAP_INT_24XX_GPIO_BANK2 30 427 # define OMAP_INT_24XX_GPIO_BANK3 31 428 # define OMAP_INT_24XX_GPIO_BANK4 32 429 # define OMAP_INT_243X_GPIO_BANK5 33 430 # define OMAP_INT_24XX_MAIL_U3_MPU 34 431 # define OMAP_INT_24XX_WDT3 35 432 # define OMAP_INT_24XX_WDT4 36 433 # define OMAP_INT_24XX_GPTIMER1 37 434 # define OMAP_INT_24XX_GPTIMER2 38 435 # define OMAP_INT_24XX_GPTIMER3 39 436 # define OMAP_INT_24XX_GPTIMER4 40 437 # define OMAP_INT_24XX_GPTIMER5 41 438 # define OMAP_INT_24XX_GPTIMER6 42 439 # define OMAP_INT_24XX_GPTIMER7 43 440 # define OMAP_INT_24XX_GPTIMER8 44 441 # define OMAP_INT_24XX_GPTIMER9 45 442 # define OMAP_INT_24XX_GPTIMER10 46 443 # define OMAP_INT_24XX_GPTIMER11 47 444 # define OMAP_INT_24XX_GPTIMER12 48 445 # define OMAP_INT_24XX_PKA_IRQ 50 446 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 447 # define OMAP_INT_24XX_RNG_IRQ 52 448 # define OMAP_INT_24XX_MG_IRQ 53 449 # define OMAP_INT_24XX_I2C1_IRQ 56 450 # define OMAP_INT_24XX_I2C2_IRQ 57 451 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 452 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 453 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 454 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 455 # define OMAP_INT_243X_MCBSP1_IRQ 64 456 # define OMAP_INT_24XX_MCSPI1_IRQ 65 457 # define OMAP_INT_24XX_MCSPI2_IRQ 66 458 # define OMAP_INT_24XX_SSI1_IRQ0 67 459 # define OMAP_INT_24XX_SSI1_IRQ1 68 460 # define OMAP_INT_24XX_SSI2_IRQ0 69 461 # define OMAP_INT_24XX_SSI2_IRQ1 70 462 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 463 # define OMAP_INT_24XX_UART1_IRQ 72 464 # define OMAP_INT_24XX_UART2_IRQ 73 465 # define OMAP_INT_24XX_UART3_IRQ 74 466 # define OMAP_INT_24XX_USB_IRQ_GEN 75 467 # define OMAP_INT_24XX_USB_IRQ_NISO 76 468 # define OMAP_INT_24XX_USB_IRQ_ISO 77 469 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 470 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 471 # define OMAP_INT_24XX_USB_IRQ_OTG 80 472 # define OMAP_INT_24XX_VLYNQ_IRQ 81 473 # define OMAP_INT_24XX_MMC_IRQ 83 474 # define OMAP_INT_24XX_MS_IRQ 84 475 # define OMAP_INT_24XX_FAC_IRQ 85 476 # define OMAP_INT_24XX_MCSPI3_IRQ 91 477 # define OMAP_INT_243X_HS_USB_MC 92 478 # define OMAP_INT_243X_HS_USB_DMA 93 479 # define OMAP_INT_243X_CARKIT 94 480 # define OMAP_INT_34XX_GPTIMER12 95 481 482 /* omap_dma.c */ 483 enum omap_dma_model { 484 omap_dma_3_0, 485 omap_dma_3_1, 486 omap_dma_3_2, 487 omap_dma_4, 488 }; 489 490 struct soc_dma_s; 491 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 492 MemoryRegion *sysmem, 493 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 494 enum omap_dma_model model); 495 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 496 MemoryRegion *sysmem, 497 struct omap_mpu_state_s *mpu, int fifo, 498 int chans, omap_clk iclk, omap_clk fclk); 499 void omap_dma_reset(struct soc_dma_s *s); 500 501 struct dma_irq_map { 502 int ih; 503 int intr; 504 }; 505 506 /* Only used in OMAP DMA 3.x gigacells */ 507 enum omap_dma_port { 508 emiff = 0, 509 emifs, 510 imif, /* omap16xx: ocp_t1 */ 511 tipb, 512 local, /* omap16xx: ocp_t2 */ 513 tipb_mpui, 514 __omap_dma_port_last, 515 }; 516 517 typedef enum { 518 constant = 0, 519 post_incremented, 520 single_index, 521 double_index, 522 } omap_dma_addressing_t; 523 524 /* Only used in OMAP DMA 3.x gigacells */ 525 struct omap_dma_lcd_channel_s { 526 enum omap_dma_port src; 527 hwaddr src_f1_top; 528 hwaddr src_f1_bottom; 529 hwaddr src_f2_top; 530 hwaddr src_f2_bottom; 531 532 /* Used in OMAP DMA 3.2 gigacell */ 533 unsigned char brust_f1; 534 unsigned char pack_f1; 535 unsigned char data_type_f1; 536 unsigned char brust_f2; 537 unsigned char pack_f2; 538 unsigned char data_type_f2; 539 unsigned char end_prog; 540 unsigned char repeat; 541 unsigned char auto_init; 542 unsigned char priority; 543 unsigned char fs; 544 unsigned char running; 545 unsigned char bs; 546 unsigned char omap_3_1_compatible_disable; 547 unsigned char dst; 548 unsigned char lch_type; 549 int16_t element_index_f1; 550 int16_t element_index_f2; 551 int32_t frame_index_f1; 552 int32_t frame_index_f2; 553 uint16_t elements_f1; 554 uint16_t frames_f1; 555 uint16_t elements_f2; 556 uint16_t frames_f2; 557 omap_dma_addressing_t mode_f1; 558 omap_dma_addressing_t mode_f2; 559 560 /* Destination port is fixed. */ 561 int interrupts; 562 int condition; 563 int dual; 564 565 int current_frame; 566 hwaddr phys_framebuffer[2]; 567 qemu_irq irq; 568 struct omap_mpu_state_s *mpu; 569 } *omap_dma_get_lcdch(struct soc_dma_s *s); 570 571 /* 572 * DMA request numbers for OMAP1 573 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 574 */ 575 # define OMAP_DMA_NO_DEVICE 0 576 # define OMAP_DMA_MCSI1_TX 1 577 # define OMAP_DMA_MCSI1_RX 2 578 # define OMAP_DMA_I2C_RX 3 579 # define OMAP_DMA_I2C_TX 4 580 # define OMAP_DMA_EXT_NDMA_REQ0 5 581 # define OMAP_DMA_EXT_NDMA_REQ1 6 582 # define OMAP_DMA_UWIRE_TX 7 583 # define OMAP_DMA_MCBSP1_TX 8 584 # define OMAP_DMA_MCBSP1_RX 9 585 # define OMAP_DMA_MCBSP3_TX 10 586 # define OMAP_DMA_MCBSP3_RX 11 587 # define OMAP_DMA_UART1_TX 12 588 # define OMAP_DMA_UART1_RX 13 589 # define OMAP_DMA_UART2_TX 14 590 # define OMAP_DMA_UART2_RX 15 591 # define OMAP_DMA_MCBSP2_TX 16 592 # define OMAP_DMA_MCBSP2_RX 17 593 # define OMAP_DMA_UART3_TX 18 594 # define OMAP_DMA_UART3_RX 19 595 # define OMAP_DMA_CAMERA_IF_RX 20 596 # define OMAP_DMA_MMC_TX 21 597 # define OMAP_DMA_MMC_RX 22 598 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 599 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 600 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 601 # define OMAP_DMA_USB_W2FC_RX0 26 602 # define OMAP_DMA_USB_W2FC_RX1 27 603 # define OMAP_DMA_USB_W2FC_RX2 28 604 # define OMAP_DMA_USB_W2FC_TX0 29 605 # define OMAP_DMA_USB_W2FC_TX1 30 606 # define OMAP_DMA_USB_W2FC_TX2 31 607 608 /* These are only for 1610 */ 609 # define OMAP_DMA_CRYPTO_DES_IN 32 610 # define OMAP_DMA_SPI_TX 33 611 # define OMAP_DMA_SPI_RX 34 612 # define OMAP_DMA_CRYPTO_HASH 35 613 # define OMAP_DMA_CCP_ATTN 36 614 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 615 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 616 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 617 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 618 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 619 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 620 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 621 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 622 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 623 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 624 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 625 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 626 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 627 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 628 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 629 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 630 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 631 # define OMAP_DMA_MMC2_TX 54 632 # define OMAP_DMA_MMC2_RX 55 633 # define OMAP_DMA_CRYPTO_DES_OUT 56 634 635 /* 636 * DMA request numbers for the OMAP2 637 */ 638 # define OMAP24XX_DMA_NO_DEVICE 0 639 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 640 # define OMAP24XX_DMA_EXT_DMAREQ0 2 641 # define OMAP24XX_DMA_EXT_DMAREQ1 3 642 # define OMAP24XX_DMA_GPMC 4 643 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 644 # define OMAP24XX_DMA_DSS 6 645 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 646 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 647 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 648 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 649 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 651 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 652 # define OMAP24XX_DMA_EXT_DMAREQ2 14 653 # define OMAP24XX_DMA_EXT_DMAREQ3 15 654 # define OMAP24XX_DMA_EXT_DMAREQ4 16 655 # define OMAP24XX_DMA_EAC_AC_RD 17 656 # define OMAP24XX_DMA_EAC_AC_WR 18 657 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 658 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 659 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 660 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 661 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 662 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 663 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 664 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 665 # define OMAP24XX_DMA_I2C1_TX 27 666 # define OMAP24XX_DMA_I2C1_RX 28 667 # define OMAP24XX_DMA_I2C2_TX 29 668 # define OMAP24XX_DMA_I2C2_RX 30 669 # define OMAP24XX_DMA_MCBSP1_TX 31 670 # define OMAP24XX_DMA_MCBSP1_RX 32 671 # define OMAP24XX_DMA_MCBSP2_TX 33 672 # define OMAP24XX_DMA_MCBSP2_RX 34 673 # define OMAP24XX_DMA_SPI1_TX0 35 674 # define OMAP24XX_DMA_SPI1_RX0 36 675 # define OMAP24XX_DMA_SPI1_TX1 37 676 # define OMAP24XX_DMA_SPI1_RX1 38 677 # define OMAP24XX_DMA_SPI1_TX2 39 678 # define OMAP24XX_DMA_SPI1_RX2 40 679 # define OMAP24XX_DMA_SPI1_TX3 41 680 # define OMAP24XX_DMA_SPI1_RX3 42 681 # define OMAP24XX_DMA_SPI2_TX0 43 682 # define OMAP24XX_DMA_SPI2_RX0 44 683 # define OMAP24XX_DMA_SPI2_TX1 45 684 # define OMAP24XX_DMA_SPI2_RX1 46 685 686 # define OMAP24XX_DMA_UART1_TX 49 687 # define OMAP24XX_DMA_UART1_RX 50 688 # define OMAP24XX_DMA_UART2_TX 51 689 # define OMAP24XX_DMA_UART2_RX 52 690 # define OMAP24XX_DMA_UART3_TX 53 691 # define OMAP24XX_DMA_UART3_RX 54 692 # define OMAP24XX_DMA_USB_W2FC_TX0 55 693 # define OMAP24XX_DMA_USB_W2FC_RX0 56 694 # define OMAP24XX_DMA_USB_W2FC_TX1 57 695 # define OMAP24XX_DMA_USB_W2FC_RX1 58 696 # define OMAP24XX_DMA_USB_W2FC_TX2 59 697 # define OMAP24XX_DMA_USB_W2FC_RX2 60 698 # define OMAP24XX_DMA_MMC1_TX 61 699 # define OMAP24XX_DMA_MMC1_RX 62 700 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 701 # define OMAP24XX_DMA_EXT_DMAREQ5 64 702 703 /* omap[123].c */ 704 /* OMAP2 gp timer */ 705 struct omap_gp_timer_s; 706 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 707 qemu_irq irq, omap_clk fclk, omap_clk iclk); 708 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 709 710 /* OMAP2 sysctimer */ 711 struct omap_synctimer_s; 712 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 713 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 714 void omap_synctimer_reset(struct omap_synctimer_s *s); 715 716 struct omap_uart_s; 717 struct omap_uart_s *omap_uart_init(hwaddr base, 718 qemu_irq irq, omap_clk fclk, omap_clk iclk, 719 qemu_irq txdma, qemu_irq rxdma, 720 const char *label, Chardev *chr); 721 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 722 struct omap_target_agent_s *ta, 723 qemu_irq irq, omap_clk fclk, omap_clk iclk, 724 qemu_irq txdma, qemu_irq rxdma, 725 const char *label, Chardev *chr); 726 void omap_uart_reset(struct omap_uart_s *s); 727 728 struct omap_mpuio_s; 729 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 730 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 731 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 732 733 struct omap_uwire_s; 734 void omap_uwire_attach(struct omap_uwire_s *s, 735 uWireSlave *slave, int chipselect); 736 737 /* OMAP2 spi */ 738 struct omap_mcspi_s; 739 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 740 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 741 void omap_mcspi_attach(struct omap_mcspi_s *s, 742 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 743 int chipselect); 744 void omap_mcspi_reset(struct omap_mcspi_s *s); 745 746 struct I2SCodec { 747 void *opaque; 748 749 /* The CPU can call this if it is generating the clock signal on the 750 * i2s port. The CODEC can ignore it if it is set up as a clock 751 * master and generates its own clock. */ 752 void (*set_rate)(void *opaque, int in, int out); 753 754 void (*tx_swallow)(void *opaque); 755 qemu_irq rx_swallow; 756 qemu_irq tx_start; 757 758 int tx_rate; 759 int cts; 760 int rx_rate; 761 int rts; 762 763 struct i2s_fifo_s { 764 uint8_t *fifo; 765 int len; 766 int start; 767 int size; 768 } in, out; 769 }; 770 struct omap_mcbsp_s; 771 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 772 773 void omap_tap_init(struct omap_target_agent_s *ta, 774 struct omap_mpu_state_s *mpu); 775 776 /* omap_lcdc.c */ 777 struct omap_lcd_panel_s; 778 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 779 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 780 hwaddr base, 781 qemu_irq irq, 782 struct omap_dma_lcd_channel_s *dma, 783 omap_clk clk); 784 785 /* omap_dss.c */ 786 struct rfbi_chip_s { 787 void *opaque; 788 void (*write)(void *opaque, int dc, uint16_t value); 789 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 790 uint16_t (*read)(void *opaque, int dc); 791 }; 792 struct omap_dss_s; 793 void omap_dss_reset(struct omap_dss_s *s); 794 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 795 MemoryRegion *sysmem, 796 hwaddr l3_base, 797 qemu_irq irq, qemu_irq drq, 798 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 799 omap_clk ick1, omap_clk ick2); 800 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 801 802 /* omap_mmc.c */ 803 struct omap_mmc_s; 804 struct omap_mmc_s *omap_mmc_init(hwaddr base, 805 MemoryRegion *sysmem, 806 BlockBackend *blk, 807 qemu_irq irq, qemu_irq dma[], omap_clk clk); 808 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 809 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 810 omap_clk fclk, omap_clk iclk); 811 void omap_mmc_reset(struct omap_mmc_s *s); 812 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 813 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 814 815 /* omap_i2c.c */ 816 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 817 818 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 819 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 820 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 821 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 822 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 823 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 824 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 825 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 826 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 827 828 # define cpu_is_omap15xx(cpu) \ 829 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 830 # define cpu_is_omap16xx(cpu) \ 831 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 832 # define cpu_is_omap24xx(cpu) \ 833 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 834 835 # define cpu_class_omap1(cpu) \ 836 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 837 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 838 # define cpu_class_omap3(cpu) \ 839 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 840 841 struct omap_mpu_state_s { 842 enum omap_mpu_model { 843 omap310, 844 omap1510, 845 omap1610, 846 omap1710, 847 omap2410, 848 omap2420, 849 omap2422, 850 omap2423, 851 omap2430, 852 omap3430, 853 omap3630, 854 } mpu_model; 855 856 ARMCPU *cpu; 857 858 qemu_irq *drq; 859 860 qemu_irq wakeup; 861 862 MemoryRegion ulpd_pm_iomem; 863 MemoryRegion pin_cfg_iomem; 864 MemoryRegion id_iomem; 865 MemoryRegion id_iomem_e18; 866 MemoryRegion id_iomem_ed4; 867 MemoryRegion id_iomem_e20; 868 MemoryRegion mpui_iomem; 869 MemoryRegion tcmi_iomem; 870 MemoryRegion clkm_iomem; 871 MemoryRegion clkdsp_iomem; 872 MemoryRegion mpui_io_iomem; 873 MemoryRegion tap_iomem; 874 MemoryRegion imif_ram; 875 MemoryRegion sram; 876 877 struct omap_dma_port_if_s { 878 uint32_t (*read[3])(struct omap_mpu_state_s *s, 879 hwaddr offset); 880 void (*write[3])(struct omap_mpu_state_s *s, 881 hwaddr offset, uint32_t value); 882 int (*addr_valid)(struct omap_mpu_state_s *s, 883 hwaddr addr); 884 } port[__omap_dma_port_last]; 885 886 uint64_t sdram_size; 887 unsigned long sram_size; 888 889 /* MPUI-TIPB peripherals */ 890 struct omap_uart_s *uart[3]; 891 892 DeviceState *gpio; 893 894 struct omap_mcbsp_s *mcbsp1; 895 struct omap_mcbsp_s *mcbsp3; 896 897 /* MPU public TIPB peripherals */ 898 struct omap_32khz_timer_s *os_timer; 899 900 struct omap_mmc_s *mmc; 901 902 struct omap_mpuio_s *mpuio; 903 904 struct omap_uwire_s *microwire; 905 906 struct omap_pwl_s *pwl; 907 struct omap_pwt_s *pwt; 908 DeviceState *i2c[2]; 909 910 struct omap_rtc_s *rtc; 911 912 struct omap_mcbsp_s *mcbsp2; 913 914 struct omap_lpg_s *led[2]; 915 916 /* MPU private TIPB peripherals */ 917 DeviceState *ih[2]; 918 919 struct soc_dma_s *dma; 920 921 struct omap_mpu_timer_s *timer[3]; 922 struct omap_watchdog_timer_s *wdt; 923 924 struct omap_lcd_panel_s *lcd; 925 926 uint32_t ulpd_pm_regs[21]; 927 int64_t ulpd_gauge_start; 928 929 uint32_t func_mux_ctrl[14]; 930 uint32_t comp_mode_ctrl[1]; 931 uint32_t pull_dwn_ctrl[4]; 932 uint32_t gate_inh_ctrl[1]; 933 uint32_t voltage_ctrl[1]; 934 uint32_t test_dbg_ctrl[1]; 935 uint32_t mod_conf_ctrl[1]; 936 int compat1509; 937 938 uint32_t mpui_ctrl; 939 940 struct omap_tipb_bridge_s *private_tipb; 941 struct omap_tipb_bridge_s *public_tipb; 942 943 uint32_t tcmi_regs[17]; 944 945 struct dpll_ctl_s *dpll[3]; 946 947 omap_clk clks; 948 struct { 949 int cold_start; 950 int clocking_scheme; 951 uint16_t arm_ckctl; 952 uint16_t arm_idlect1; 953 uint16_t arm_idlect2; 954 uint16_t arm_ewupct; 955 uint16_t arm_rstct1; 956 uint16_t arm_rstct2; 957 uint16_t arm_ckout1; 958 int dpll1_mode; 959 uint16_t dsp_idlect1; 960 uint16_t dsp_idlect2; 961 uint16_t dsp_rstct2; 962 } clkm; 963 964 /* OMAP2-only peripherals */ 965 struct omap_l4_s *l4; 966 967 struct omap_gp_timer_s *gptimer[12]; 968 struct omap_synctimer_s *synctimer; 969 970 struct omap_prcm_s *prcm; 971 struct omap_sdrc_s *sdrc; 972 struct omap_gpmc_s *gpmc; 973 struct omap_sysctl_s *sysc; 974 975 struct omap_mcspi_s *mcspi[2]; 976 977 struct omap_dss_s *dss; 978 979 struct omap_eac_s *eac; 980 }; 981 982 /* omap1.c */ 983 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 984 const char *core); 985 986 /* omap2.c */ 987 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 988 const char *core); 989 990 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 991 void omap_badwidth_write8(void *opaque, hwaddr addr, 992 uint32_t value); 993 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 994 void omap_badwidth_write16(void *opaque, hwaddr addr, 995 uint32_t value); 996 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 997 void omap_badwidth_write32(void *opaque, hwaddr addr, 998 uint32_t value); 999 1000 void omap_mpu_wakeup(void *opaque, int irq, int req); 1001 1002 # define OMAP_BAD_REG(paddr) \ 1003 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1004 __func__, paddr) 1005 # define OMAP_RO_REG(paddr) \ 1006 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 1007 HWADDR_PRIx "\n", \ 1008 __func__, paddr) 1009 1010 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1011 (Board-specifc tags are not here) */ 1012 #define OMAP_TAG_CLOCK 0x4f01 1013 #define OMAP_TAG_MMC 0x4f02 1014 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1015 #define OMAP_TAG_USB 0x4f04 1016 #define OMAP_TAG_LCD 0x4f05 1017 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1018 #define OMAP_TAG_UART 0x4f07 1019 #define OMAP_TAG_FBMEM 0x4f08 1020 #define OMAP_TAG_STI_CONSOLE 0x4f09 1021 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1022 #define OMAP_TAG_PARTITION 0x4f0b 1023 #define OMAP_TAG_TEA5761 0x4f10 1024 #define OMAP_TAG_TMP105 0x4f11 1025 #define OMAP_TAG_BOOT_REASON 0x4f80 1026 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1027 #define OMAP_TAG_VERSION_STR 0x4f82 1028 1029 enum { 1030 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1031 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1032 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1033 }; 1034 1035 #define OMAP_GPIOSW_INVERTED 0x0001 1036 #define OMAP_GPIOSW_OUTPUT 0x0002 1037 1038 # define OMAP_MPUI_REG_MASK 0x000007ff 1039 1040 #endif 1041