1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "hw/input/tsc2xxx.h" 25 #include "target/arm/cpu-qom.h" 26 #include "qemu/log.h" 27 #include "qom/object.h" 28 29 # define OMAP_EMIFS_BASE 0x00000000 30 # define OMAP2_Q0_BASE 0x00000000 31 # define OMAP_CS0_BASE 0x00000000 32 # define OMAP_CS1_BASE 0x04000000 33 # define OMAP_CS2_BASE 0x08000000 34 # define OMAP_CS3_BASE 0x0c000000 35 # define OMAP_EMIFF_BASE 0x10000000 36 # define OMAP_IMIF_BASE 0x20000000 37 # define OMAP_LOCALBUS_BASE 0x30000000 38 # define OMAP2_Q1_BASE 0x40000000 39 # define OMAP2_L4_BASE 0x48000000 40 # define OMAP2_SRAM_BASE 0x40200000 41 # define OMAP2_L3_BASE 0x68000000 42 # define OMAP2_Q2_BASE 0x80000000 43 # define OMAP2_Q3_BASE 0xc0000000 44 # define OMAP_MPUI_BASE 0xe1000000 45 46 # define OMAP730_SRAM_SIZE 0x00032000 47 # define OMAP15XX_SRAM_SIZE 0x00030000 48 # define OMAP16XX_SRAM_SIZE 0x00004000 49 # define OMAP1611_SRAM_SIZE 0x0003e800 50 # define OMAP242X_SRAM_SIZE 0x000a0000 51 # define OMAP243X_SRAM_SIZE 0x00010000 52 # define OMAP_CS0_SIZE 0x04000000 53 # define OMAP_CS1_SIZE 0x04000000 54 # define OMAP_CS2_SIZE 0x04000000 55 # define OMAP_CS3_SIZE 0x04000000 56 57 /* omap_clk.c */ 58 struct omap_mpu_state_s; 59 typedef struct clk *omap_clk; 60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 61 void omap_clk_init(struct omap_mpu_state_s *mpu); 62 void omap_clk_adduser(struct clk *clk, qemu_irq user); 63 void omap_clk_get(omap_clk clk); 64 void omap_clk_put(omap_clk clk); 65 void omap_clk_onoff(omap_clk clk, int on); 66 void omap_clk_canidle(omap_clk clk, int can); 67 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 68 int64_t omap_clk_getrate(omap_clk clk); 69 void omap_clk_reparent(omap_clk clk, omap_clk parent); 70 71 /* omap_intc.c */ 72 #define TYPE_OMAP_INTC "common-omap-intc" 73 typedef struct omap_intr_handler_s omap_intr_handler; 74 DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC, 75 TYPE_OMAP_INTC) 76 77 78 /* 79 * TODO: Ideally we should have a clock framework that 80 * let us wire these clocks up with QOM properties or links. 81 * 82 * qdev should support a generic means of defining a 'port' with 83 * an arbitrary interface for connecting two devices. Then we 84 * could reframe the omap clock API in terms of clock ports, 85 * and get some type safety. For now the best qdev provides is 86 * passing an arbitrary pointer. 87 * (It's not possible to pass in the string which is the clock 88 * name, because this device does not have the necessary information 89 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 90 * translation.) 91 */ 92 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); 93 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); 94 95 /* omap_i2c.c */ 96 #define TYPE_OMAP_I2C "omap_i2c" 97 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 98 99 100 /* TODO: clock framework (see above) */ 101 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 102 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 103 104 /* omap_gpio.c */ 105 #define TYPE_OMAP1_GPIO "omap-gpio" 106 typedef struct Omap1GpioState Omap1GpioState; 107 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 108 TYPE_OMAP1_GPIO) 109 110 #define TYPE_OMAP2_GPIO "omap2-gpio" 111 typedef struct Omap2GpioState Omap2GpioState; 112 DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO, 113 TYPE_OMAP2_GPIO) 114 115 /* TODO: clock framework (see above) */ 116 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 117 118 void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk); 119 void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk); 120 121 /* OMAP2 l4 Interconnect */ 122 struct omap_l4_s; 123 struct omap_l4_region_s { 124 hwaddr offset; 125 size_t size; 126 int access; 127 }; 128 struct omap_l4_agent_info_s { 129 int ta; 130 int region; 131 int regions; 132 int ta_region; 133 }; 134 struct omap_target_agent_s { 135 MemoryRegion iomem; 136 struct omap_l4_s *bus; 137 int regions; 138 const struct omap_l4_region_s *start; 139 hwaddr base; 140 uint32_t component; 141 uint32_t control; 142 uint32_t status; 143 }; 144 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 145 hwaddr base, int ta_num); 146 147 struct omap_target_agent_s; 148 struct omap_target_agent_s *omap_l4ta_get( 149 struct omap_l4_s *bus, 150 const struct omap_l4_region_s *regions, 151 const struct omap_l4_agent_info_s *agents, 152 int cs); 153 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 154 int region, MemoryRegion *mr); 155 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 156 int region); 157 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 158 int region); 159 160 /* OMAP2 SDRAM controller */ 161 struct omap_sdrc_s; 162 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 163 hwaddr base); 164 void omap_sdrc_reset(struct omap_sdrc_s *s); 165 166 /* OMAP2 general purpose memory controller */ 167 struct omap_gpmc_s; 168 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 169 hwaddr base, 170 qemu_irq irq, qemu_irq drq); 171 void omap_gpmc_reset(struct omap_gpmc_s *s); 172 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 173 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 174 175 /* 176 * Common IRQ numbers for level 1 interrupt handler 177 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 178 */ 179 # define OMAP_INT_CAMERA 1 180 # define OMAP_INT_FIQ 3 181 # define OMAP_INT_RTDX 6 182 # define OMAP_INT_DSP_MMU_ABORT 7 183 # define OMAP_INT_HOST 8 184 # define OMAP_INT_ABORT 9 185 # define OMAP_INT_BRIDGE_PRIV 13 186 # define OMAP_INT_GPIO_BANK1 14 187 # define OMAP_INT_UART3 15 188 # define OMAP_INT_TIMER3 16 189 # define OMAP_INT_DMA_CH0_6 19 190 # define OMAP_INT_DMA_CH1_7 20 191 # define OMAP_INT_DMA_CH2_8 21 192 # define OMAP_INT_DMA_CH3 22 193 # define OMAP_INT_DMA_CH4 23 194 # define OMAP_INT_DMA_CH5 24 195 # define OMAP_INT_DMA_LCD 25 196 # define OMAP_INT_TIMER1 26 197 # define OMAP_INT_WD_TIMER 27 198 # define OMAP_INT_BRIDGE_PUB 28 199 # define OMAP_INT_TIMER2 30 200 # define OMAP_INT_LCD_CTRL 31 201 202 /* 203 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 204 */ 205 # define OMAP_INT_15XX_IH2_IRQ 0 206 # define OMAP_INT_15XX_LB_MMU 17 207 # define OMAP_INT_15XX_LOCAL_BUS 29 208 209 /* 210 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 211 */ 212 # define OMAP_INT_1510_SPI_TX 4 213 # define OMAP_INT_1510_SPI_RX 5 214 # define OMAP_INT_1510_DSP_MAILBOX1 10 215 # define OMAP_INT_1510_DSP_MAILBOX2 11 216 217 /* 218 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 219 */ 220 # define OMAP_INT_310_McBSP2_TX 4 221 # define OMAP_INT_310_McBSP2_RX 5 222 # define OMAP_INT_310_HSB_MAILBOX1 12 223 # define OMAP_INT_310_HSAB_MMU 18 224 225 /* 226 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 227 */ 228 # define OMAP_INT_1610_IH2_IRQ 0 229 # define OMAP_INT_1610_IH2_FIQ 2 230 # define OMAP_INT_1610_McBSP2_TX 4 231 # define OMAP_INT_1610_McBSP2_RX 5 232 # define OMAP_INT_1610_DSP_MAILBOX1 10 233 # define OMAP_INT_1610_DSP_MAILBOX2 11 234 # define OMAP_INT_1610_LCD_LINE 12 235 # define OMAP_INT_1610_GPTIMER1 17 236 # define OMAP_INT_1610_GPTIMER2 18 237 # define OMAP_INT_1610_SSR_FIFO_0 29 238 239 /* 240 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 241 */ 242 # define OMAP_INT_730_IH2_FIQ 0 243 # define OMAP_INT_730_IH2_IRQ 1 244 # define OMAP_INT_730_USB_NON_ISO 2 245 # define OMAP_INT_730_USB_ISO 3 246 # define OMAP_INT_730_ICR 4 247 # define OMAP_INT_730_EAC 5 248 # define OMAP_INT_730_GPIO_BANK1 6 249 # define OMAP_INT_730_GPIO_BANK2 7 250 # define OMAP_INT_730_GPIO_BANK3 8 251 # define OMAP_INT_730_McBSP2TX 10 252 # define OMAP_INT_730_McBSP2RX 11 253 # define OMAP_INT_730_McBSP2RX_OVF 12 254 # define OMAP_INT_730_LCD_LINE 14 255 # define OMAP_INT_730_GSM_PROTECT 15 256 # define OMAP_INT_730_TIMER3 16 257 # define OMAP_INT_730_GPIO_BANK5 17 258 # define OMAP_INT_730_GPIO_BANK6 18 259 # define OMAP_INT_730_SPGIO_WR 29 260 261 /* 262 * Common IRQ numbers for level 2 interrupt handler 263 */ 264 # define OMAP_INT_KEYBOARD 1 265 # define OMAP_INT_uWireTX 2 266 # define OMAP_INT_uWireRX 3 267 # define OMAP_INT_I2C 4 268 # define OMAP_INT_MPUIO 5 269 # define OMAP_INT_USB_HHC_1 6 270 # define OMAP_INT_McBSP3TX 10 271 # define OMAP_INT_McBSP3RX 11 272 # define OMAP_INT_McBSP1TX 12 273 # define OMAP_INT_McBSP1RX 13 274 # define OMAP_INT_UART1 14 275 # define OMAP_INT_UART2 15 276 # define OMAP_INT_USB_W2FC 20 277 # define OMAP_INT_1WIRE 21 278 # define OMAP_INT_OS_TIMER 22 279 # define OMAP_INT_OQN 23 280 # define OMAP_INT_GAUGE_32K 24 281 # define OMAP_INT_RTC_TIMER 25 282 # define OMAP_INT_RTC_ALARM 26 283 # define OMAP_INT_DSP_MMU 28 284 285 /* 286 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 287 */ 288 # define OMAP_INT_1510_BT_MCSI1TX 16 289 # define OMAP_INT_1510_BT_MCSI1RX 17 290 # define OMAP_INT_1510_SoSSI_MATCH 19 291 # define OMAP_INT_1510_MEM_STICK 27 292 # define OMAP_INT_1510_COM_SPI_RO 31 293 294 /* 295 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 296 */ 297 # define OMAP_INT_310_FAC 0 298 # define OMAP_INT_310_USB_HHC_2 7 299 # define OMAP_INT_310_MCSI1_FE 16 300 # define OMAP_INT_310_MCSI2_FE 17 301 # define OMAP_INT_310_USB_W2FC_ISO 29 302 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 303 # define OMAP_INT_310_McBSP2RX_OF 31 304 305 /* 306 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 307 */ 308 # define OMAP_INT_1610_FAC 0 309 # define OMAP_INT_1610_USB_HHC_2 7 310 # define OMAP_INT_1610_USB_OTG 8 311 # define OMAP_INT_1610_SoSSI 9 312 # define OMAP_INT_1610_BT_MCSI1TX 16 313 # define OMAP_INT_1610_BT_MCSI1RX 17 314 # define OMAP_INT_1610_SoSSI_MATCH 19 315 # define OMAP_INT_1610_MEM_STICK 27 316 # define OMAP_INT_1610_McBSP2RX_OF 31 317 # define OMAP_INT_1610_STI 32 318 # define OMAP_INT_1610_STI_WAKEUP 33 319 # define OMAP_INT_1610_GPTIMER3 34 320 # define OMAP_INT_1610_GPTIMER4 35 321 # define OMAP_INT_1610_GPTIMER5 36 322 # define OMAP_INT_1610_GPTIMER6 37 323 # define OMAP_INT_1610_GPTIMER7 38 324 # define OMAP_INT_1610_GPTIMER8 39 325 # define OMAP_INT_1610_GPIO_BANK2 40 326 # define OMAP_INT_1610_GPIO_BANK3 41 327 # define OMAP_INT_1610_MMC2 42 328 # define OMAP_INT_1610_CF 43 329 # define OMAP_INT_1610_WAKE_UP_REQ 46 330 # define OMAP_INT_1610_GPIO_BANK4 48 331 # define OMAP_INT_1610_SPI 49 332 # define OMAP_INT_1610_DMA_CH6 53 333 # define OMAP_INT_1610_DMA_CH7 54 334 # define OMAP_INT_1610_DMA_CH8 55 335 # define OMAP_INT_1610_DMA_CH9 56 336 # define OMAP_INT_1610_DMA_CH10 57 337 # define OMAP_INT_1610_DMA_CH11 58 338 # define OMAP_INT_1610_DMA_CH12 59 339 # define OMAP_INT_1610_DMA_CH13 60 340 # define OMAP_INT_1610_DMA_CH14 61 341 # define OMAP_INT_1610_DMA_CH15 62 342 # define OMAP_INT_1610_NAND 63 343 344 /* 345 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 346 */ 347 # define OMAP_INT_730_HW_ERRORS 0 348 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 349 # define OMAP_INT_730_CFCD 2 350 # define OMAP_INT_730_CFIREQ 3 351 # define OMAP_INT_730_I2C 4 352 # define OMAP_INT_730_PCC 5 353 # define OMAP_INT_730_MPU_EXT_NIRQ 6 354 # define OMAP_INT_730_SPI_100K_1 7 355 # define OMAP_INT_730_SYREN_SPI 8 356 # define OMAP_INT_730_VLYNQ 9 357 # define OMAP_INT_730_GPIO_BANK4 10 358 # define OMAP_INT_730_McBSP1TX 11 359 # define OMAP_INT_730_McBSP1RX 12 360 # define OMAP_INT_730_McBSP1RX_OF 13 361 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 362 # define OMAP_INT_730_UART_MODEM_1 15 363 # define OMAP_INT_730_MCSI 16 364 # define OMAP_INT_730_uWireTX 17 365 # define OMAP_INT_730_uWireRX 18 366 # define OMAP_INT_730_SMC_CD 19 367 # define OMAP_INT_730_SMC_IREQ 20 368 # define OMAP_INT_730_HDQ_1WIRE 21 369 # define OMAP_INT_730_TIMER32K 22 370 # define OMAP_INT_730_MMC_SDIO 23 371 # define OMAP_INT_730_UPLD 24 372 # define OMAP_INT_730_USB_HHC_1 27 373 # define OMAP_INT_730_USB_HHC_2 28 374 # define OMAP_INT_730_USB_GENI 29 375 # define OMAP_INT_730_USB_OTG 30 376 # define OMAP_INT_730_CAMERA_IF 31 377 # define OMAP_INT_730_RNG 32 378 # define OMAP_INT_730_DUAL_MODE_TIMER 33 379 # define OMAP_INT_730_DBB_RF_EN 34 380 # define OMAP_INT_730_MPUIO_KEYPAD 35 381 # define OMAP_INT_730_SHA1_MD5 36 382 # define OMAP_INT_730_SPI_100K_2 37 383 # define OMAP_INT_730_RNG_IDLE 38 384 # define OMAP_INT_730_MPUIO 39 385 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 386 # define OMAP_INT_730_LLPC_OE_FALLING 41 387 # define OMAP_INT_730_LLPC_OE_RISING 42 388 # define OMAP_INT_730_LLPC_VSYNC 43 389 # define OMAP_INT_730_WAKE_UP_REQ 46 390 # define OMAP_INT_730_DMA_CH6 53 391 # define OMAP_INT_730_DMA_CH7 54 392 # define OMAP_INT_730_DMA_CH8 55 393 # define OMAP_INT_730_DMA_CH9 56 394 # define OMAP_INT_730_DMA_CH10 57 395 # define OMAP_INT_730_DMA_CH11 58 396 # define OMAP_INT_730_DMA_CH12 59 397 # define OMAP_INT_730_DMA_CH13 60 398 # define OMAP_INT_730_DMA_CH14 61 399 # define OMAP_INT_730_DMA_CH15 62 400 # define OMAP_INT_730_NAND 63 401 402 /* 403 * OMAP-24xx common IRQ numbers 404 */ 405 # define OMAP_INT_24XX_STI 4 406 # define OMAP_INT_24XX_SYS_NIRQ 7 407 # define OMAP_INT_24XX_L3_IRQ 10 408 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 409 # define OMAP_INT_24XX_SDMA_IRQ0 12 410 # define OMAP_INT_24XX_SDMA_IRQ1 13 411 # define OMAP_INT_24XX_SDMA_IRQ2 14 412 # define OMAP_INT_24XX_SDMA_IRQ3 15 413 # define OMAP_INT_243X_MCBSP2_IRQ 16 414 # define OMAP_INT_243X_MCBSP3_IRQ 17 415 # define OMAP_INT_243X_MCBSP4_IRQ 18 416 # define OMAP_INT_243X_MCBSP5_IRQ 19 417 # define OMAP_INT_24XX_GPMC_IRQ 20 418 # define OMAP_INT_24XX_GUFFAW_IRQ 21 419 # define OMAP_INT_24XX_IVA_IRQ 22 420 # define OMAP_INT_24XX_EAC_IRQ 23 421 # define OMAP_INT_24XX_CAM_IRQ 24 422 # define OMAP_INT_24XX_DSS_IRQ 25 423 # define OMAP_INT_24XX_MAIL_U0_MPU 26 424 # define OMAP_INT_24XX_DSP_UMA 27 425 # define OMAP_INT_24XX_DSP_MMU 28 426 # define OMAP_INT_24XX_GPIO_BANK1 29 427 # define OMAP_INT_24XX_GPIO_BANK2 30 428 # define OMAP_INT_24XX_GPIO_BANK3 31 429 # define OMAP_INT_24XX_GPIO_BANK4 32 430 # define OMAP_INT_243X_GPIO_BANK5 33 431 # define OMAP_INT_24XX_MAIL_U3_MPU 34 432 # define OMAP_INT_24XX_WDT3 35 433 # define OMAP_INT_24XX_WDT4 36 434 # define OMAP_INT_24XX_GPTIMER1 37 435 # define OMAP_INT_24XX_GPTIMER2 38 436 # define OMAP_INT_24XX_GPTIMER3 39 437 # define OMAP_INT_24XX_GPTIMER4 40 438 # define OMAP_INT_24XX_GPTIMER5 41 439 # define OMAP_INT_24XX_GPTIMER6 42 440 # define OMAP_INT_24XX_GPTIMER7 43 441 # define OMAP_INT_24XX_GPTIMER8 44 442 # define OMAP_INT_24XX_GPTIMER9 45 443 # define OMAP_INT_24XX_GPTIMER10 46 444 # define OMAP_INT_24XX_GPTIMER11 47 445 # define OMAP_INT_24XX_GPTIMER12 48 446 # define OMAP_INT_24XX_PKA_IRQ 50 447 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 448 # define OMAP_INT_24XX_RNG_IRQ 52 449 # define OMAP_INT_24XX_MG_IRQ 53 450 # define OMAP_INT_24XX_I2C1_IRQ 56 451 # define OMAP_INT_24XX_I2C2_IRQ 57 452 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 453 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 454 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 455 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 456 # define OMAP_INT_243X_MCBSP1_IRQ 64 457 # define OMAP_INT_24XX_MCSPI1_IRQ 65 458 # define OMAP_INT_24XX_MCSPI2_IRQ 66 459 # define OMAP_INT_24XX_SSI1_IRQ0 67 460 # define OMAP_INT_24XX_SSI1_IRQ1 68 461 # define OMAP_INT_24XX_SSI2_IRQ0 69 462 # define OMAP_INT_24XX_SSI2_IRQ1 70 463 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 464 # define OMAP_INT_24XX_UART1_IRQ 72 465 # define OMAP_INT_24XX_UART2_IRQ 73 466 # define OMAP_INT_24XX_UART3_IRQ 74 467 # define OMAP_INT_24XX_USB_IRQ_GEN 75 468 # define OMAP_INT_24XX_USB_IRQ_NISO 76 469 # define OMAP_INT_24XX_USB_IRQ_ISO 77 470 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 471 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 472 # define OMAP_INT_24XX_USB_IRQ_OTG 80 473 # define OMAP_INT_24XX_VLYNQ_IRQ 81 474 # define OMAP_INT_24XX_MMC_IRQ 83 475 # define OMAP_INT_24XX_MS_IRQ 84 476 # define OMAP_INT_24XX_FAC_IRQ 85 477 # define OMAP_INT_24XX_MCSPI3_IRQ 91 478 # define OMAP_INT_243X_HS_USB_MC 92 479 # define OMAP_INT_243X_HS_USB_DMA 93 480 # define OMAP_INT_243X_CARKIT 94 481 # define OMAP_INT_34XX_GPTIMER12 95 482 483 /* omap_dma.c */ 484 enum omap_dma_model { 485 omap_dma_3_0, 486 omap_dma_3_1, 487 omap_dma_3_2, 488 omap_dma_4, 489 }; 490 491 struct soc_dma_s; 492 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 493 MemoryRegion *sysmem, 494 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 495 enum omap_dma_model model); 496 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 497 MemoryRegion *sysmem, 498 struct omap_mpu_state_s *mpu, int fifo, 499 int chans, omap_clk iclk, omap_clk fclk); 500 void omap_dma_reset(struct soc_dma_s *s); 501 502 struct dma_irq_map { 503 int ih; 504 int intr; 505 }; 506 507 /* Only used in OMAP DMA 3.x gigacells */ 508 enum omap_dma_port { 509 emiff = 0, 510 emifs, 511 imif, /* omap16xx: ocp_t1 */ 512 tipb, 513 local, /* omap16xx: ocp_t2 */ 514 tipb_mpui, 515 __omap_dma_port_last, 516 }; 517 518 typedef enum { 519 constant = 0, 520 post_incremented, 521 single_index, 522 double_index, 523 } omap_dma_addressing_t; 524 525 /* Only used in OMAP DMA 3.x gigacells */ 526 struct omap_dma_lcd_channel_s { 527 enum omap_dma_port src; 528 hwaddr src_f1_top; 529 hwaddr src_f1_bottom; 530 hwaddr src_f2_top; 531 hwaddr src_f2_bottom; 532 533 /* Used in OMAP DMA 3.2 gigacell */ 534 unsigned char brust_f1; 535 unsigned char pack_f1; 536 unsigned char data_type_f1; 537 unsigned char brust_f2; 538 unsigned char pack_f2; 539 unsigned char data_type_f2; 540 unsigned char end_prog; 541 unsigned char repeat; 542 unsigned char auto_init; 543 unsigned char priority; 544 unsigned char fs; 545 unsigned char running; 546 unsigned char bs; 547 unsigned char omap_3_1_compatible_disable; 548 unsigned char dst; 549 unsigned char lch_type; 550 int16_t element_index_f1; 551 int16_t element_index_f2; 552 int32_t frame_index_f1; 553 int32_t frame_index_f2; 554 uint16_t elements_f1; 555 uint16_t frames_f1; 556 uint16_t elements_f2; 557 uint16_t frames_f2; 558 omap_dma_addressing_t mode_f1; 559 omap_dma_addressing_t mode_f2; 560 561 /* Destination port is fixed. */ 562 int interrupts; 563 int condition; 564 int dual; 565 566 int current_frame; 567 hwaddr phys_framebuffer[2]; 568 qemu_irq irq; 569 struct omap_mpu_state_s *mpu; 570 } *omap_dma_get_lcdch(struct soc_dma_s *s); 571 572 /* 573 * DMA request numbers for OMAP1 574 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 575 */ 576 # define OMAP_DMA_NO_DEVICE 0 577 # define OMAP_DMA_MCSI1_TX 1 578 # define OMAP_DMA_MCSI1_RX 2 579 # define OMAP_DMA_I2C_RX 3 580 # define OMAP_DMA_I2C_TX 4 581 # define OMAP_DMA_EXT_NDMA_REQ0 5 582 # define OMAP_DMA_EXT_NDMA_REQ1 6 583 # define OMAP_DMA_UWIRE_TX 7 584 # define OMAP_DMA_MCBSP1_TX 8 585 # define OMAP_DMA_MCBSP1_RX 9 586 # define OMAP_DMA_MCBSP3_TX 10 587 # define OMAP_DMA_MCBSP3_RX 11 588 # define OMAP_DMA_UART1_TX 12 589 # define OMAP_DMA_UART1_RX 13 590 # define OMAP_DMA_UART2_TX 14 591 # define OMAP_DMA_UART2_RX 15 592 # define OMAP_DMA_MCBSP2_TX 16 593 # define OMAP_DMA_MCBSP2_RX 17 594 # define OMAP_DMA_UART3_TX 18 595 # define OMAP_DMA_UART3_RX 19 596 # define OMAP_DMA_CAMERA_IF_RX 20 597 # define OMAP_DMA_MMC_TX 21 598 # define OMAP_DMA_MMC_RX 22 599 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 600 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 601 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 602 # define OMAP_DMA_USB_W2FC_RX0 26 603 # define OMAP_DMA_USB_W2FC_RX1 27 604 # define OMAP_DMA_USB_W2FC_RX2 28 605 # define OMAP_DMA_USB_W2FC_TX0 29 606 # define OMAP_DMA_USB_W2FC_TX1 30 607 # define OMAP_DMA_USB_W2FC_TX2 31 608 609 /* These are only for 1610 */ 610 # define OMAP_DMA_CRYPTO_DES_IN 32 611 # define OMAP_DMA_SPI_TX 33 612 # define OMAP_DMA_SPI_RX 34 613 # define OMAP_DMA_CRYPTO_HASH 35 614 # define OMAP_DMA_CCP_ATTN 36 615 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 616 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 617 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 618 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 619 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 620 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 621 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 622 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 623 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 624 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 625 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 626 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 627 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 628 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 629 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 630 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 631 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 632 # define OMAP_DMA_MMC2_TX 54 633 # define OMAP_DMA_MMC2_RX 55 634 # define OMAP_DMA_CRYPTO_DES_OUT 56 635 636 /* 637 * DMA request numbers for the OMAP2 638 */ 639 # define OMAP24XX_DMA_NO_DEVICE 0 640 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 641 # define OMAP24XX_DMA_EXT_DMAREQ0 2 642 # define OMAP24XX_DMA_EXT_DMAREQ1 3 643 # define OMAP24XX_DMA_GPMC 4 644 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 645 # define OMAP24XX_DMA_DSS 6 646 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 647 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 648 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 649 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 651 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 652 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 653 # define OMAP24XX_DMA_EXT_DMAREQ2 14 654 # define OMAP24XX_DMA_EXT_DMAREQ3 15 655 # define OMAP24XX_DMA_EXT_DMAREQ4 16 656 # define OMAP24XX_DMA_EAC_AC_RD 17 657 # define OMAP24XX_DMA_EAC_AC_WR 18 658 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 659 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 660 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 661 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 662 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 663 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 664 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 665 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 666 # define OMAP24XX_DMA_I2C1_TX 27 667 # define OMAP24XX_DMA_I2C1_RX 28 668 # define OMAP24XX_DMA_I2C2_TX 29 669 # define OMAP24XX_DMA_I2C2_RX 30 670 # define OMAP24XX_DMA_MCBSP1_TX 31 671 # define OMAP24XX_DMA_MCBSP1_RX 32 672 # define OMAP24XX_DMA_MCBSP2_TX 33 673 # define OMAP24XX_DMA_MCBSP2_RX 34 674 # define OMAP24XX_DMA_SPI1_TX0 35 675 # define OMAP24XX_DMA_SPI1_RX0 36 676 # define OMAP24XX_DMA_SPI1_TX1 37 677 # define OMAP24XX_DMA_SPI1_RX1 38 678 # define OMAP24XX_DMA_SPI1_TX2 39 679 # define OMAP24XX_DMA_SPI1_RX2 40 680 # define OMAP24XX_DMA_SPI1_TX3 41 681 # define OMAP24XX_DMA_SPI1_RX3 42 682 # define OMAP24XX_DMA_SPI2_TX0 43 683 # define OMAP24XX_DMA_SPI2_RX0 44 684 # define OMAP24XX_DMA_SPI2_TX1 45 685 # define OMAP24XX_DMA_SPI2_RX1 46 686 687 # define OMAP24XX_DMA_UART1_TX 49 688 # define OMAP24XX_DMA_UART1_RX 50 689 # define OMAP24XX_DMA_UART2_TX 51 690 # define OMAP24XX_DMA_UART2_RX 52 691 # define OMAP24XX_DMA_UART3_TX 53 692 # define OMAP24XX_DMA_UART3_RX 54 693 # define OMAP24XX_DMA_USB_W2FC_TX0 55 694 # define OMAP24XX_DMA_USB_W2FC_RX0 56 695 # define OMAP24XX_DMA_USB_W2FC_TX1 57 696 # define OMAP24XX_DMA_USB_W2FC_RX1 58 697 # define OMAP24XX_DMA_USB_W2FC_TX2 59 698 # define OMAP24XX_DMA_USB_W2FC_RX2 60 699 # define OMAP24XX_DMA_MMC1_TX 61 700 # define OMAP24XX_DMA_MMC1_RX 62 701 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 702 # define OMAP24XX_DMA_EXT_DMAREQ5 64 703 704 /* omap[123].c */ 705 /* OMAP2 gp timer */ 706 struct omap_gp_timer_s; 707 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 708 qemu_irq irq, omap_clk fclk, omap_clk iclk); 709 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 710 711 /* OMAP2 sysctimer */ 712 struct omap_synctimer_s; 713 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 714 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 715 void omap_synctimer_reset(struct omap_synctimer_s *s); 716 717 struct omap_uart_s; 718 struct omap_uart_s *omap_uart_init(hwaddr base, 719 qemu_irq irq, omap_clk fclk, omap_clk iclk, 720 qemu_irq txdma, qemu_irq rxdma, 721 const char *label, Chardev *chr); 722 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 723 struct omap_target_agent_s *ta, 724 qemu_irq irq, omap_clk fclk, omap_clk iclk, 725 qemu_irq txdma, qemu_irq rxdma, 726 const char *label, Chardev *chr); 727 void omap_uart_reset(struct omap_uart_s *s); 728 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 729 730 struct omap_mpuio_s; 731 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 732 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 733 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 734 735 struct omap_uwire_s; 736 void omap_uwire_attach(struct omap_uwire_s *s, 737 uWireSlave *slave, int chipselect); 738 739 /* OMAP2 spi */ 740 struct omap_mcspi_s; 741 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 742 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 743 void omap_mcspi_attach(struct omap_mcspi_s *s, 744 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 745 int chipselect); 746 void omap_mcspi_reset(struct omap_mcspi_s *s); 747 748 struct I2SCodec { 749 void *opaque; 750 751 /* The CPU can call this if it is generating the clock signal on the 752 * i2s port. The CODEC can ignore it if it is set up as a clock 753 * master and generates its own clock. */ 754 void (*set_rate)(void *opaque, int in, int out); 755 756 void (*tx_swallow)(void *opaque); 757 qemu_irq rx_swallow; 758 qemu_irq tx_start; 759 760 int tx_rate; 761 int cts; 762 int rx_rate; 763 int rts; 764 765 struct i2s_fifo_s { 766 uint8_t *fifo; 767 int len; 768 int start; 769 int size; 770 } in, out; 771 }; 772 struct omap_mcbsp_s; 773 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 774 775 void omap_tap_init(struct omap_target_agent_s *ta, 776 struct omap_mpu_state_s *mpu); 777 778 /* omap_lcdc.c */ 779 struct omap_lcd_panel_s; 780 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 781 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 782 hwaddr base, 783 qemu_irq irq, 784 struct omap_dma_lcd_channel_s *dma, 785 omap_clk clk); 786 787 /* omap_dss.c */ 788 struct rfbi_chip_s { 789 void *opaque; 790 void (*write)(void *opaque, int dc, uint16_t value); 791 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 792 uint16_t (*read)(void *opaque, int dc); 793 }; 794 struct omap_dss_s; 795 void omap_dss_reset(struct omap_dss_s *s); 796 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 797 MemoryRegion *sysmem, 798 hwaddr l3_base, 799 qemu_irq irq, qemu_irq drq, 800 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 801 omap_clk ick1, omap_clk ick2); 802 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 803 804 /* omap_mmc.c */ 805 struct omap_mmc_s; 806 struct omap_mmc_s *omap_mmc_init(hwaddr base, 807 MemoryRegion *sysmem, 808 BlockBackend *blk, 809 qemu_irq irq, qemu_irq dma[], omap_clk clk); 810 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 811 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 812 omap_clk fclk, omap_clk iclk); 813 void omap_mmc_reset(struct omap_mmc_s *s); 814 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 815 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 816 817 /* omap_i2c.c */ 818 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 819 820 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 821 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 822 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 823 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 824 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 825 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 826 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 827 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 828 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 829 830 # define cpu_is_omap15xx(cpu) \ 831 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 832 # define cpu_is_omap16xx(cpu) \ 833 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 834 # define cpu_is_omap24xx(cpu) \ 835 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 836 837 # define cpu_class_omap1(cpu) \ 838 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 839 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 840 # define cpu_class_omap3(cpu) \ 841 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 842 843 struct omap_mpu_state_s { 844 enum omap_mpu_model { 845 omap310, 846 omap1510, 847 omap1610, 848 omap1710, 849 omap2410, 850 omap2420, 851 omap2422, 852 omap2423, 853 omap2430, 854 omap3430, 855 omap3630, 856 } mpu_model; 857 858 ARMCPU *cpu; 859 860 qemu_irq *drq; 861 862 qemu_irq wakeup; 863 864 MemoryRegion ulpd_pm_iomem; 865 MemoryRegion pin_cfg_iomem; 866 MemoryRegion id_iomem; 867 MemoryRegion id_iomem_e18; 868 MemoryRegion id_iomem_ed4; 869 MemoryRegion id_iomem_e20; 870 MemoryRegion mpui_iomem; 871 MemoryRegion tcmi_iomem; 872 MemoryRegion clkm_iomem; 873 MemoryRegion clkdsp_iomem; 874 MemoryRegion mpui_io_iomem; 875 MemoryRegion tap_iomem; 876 MemoryRegion imif_ram; 877 MemoryRegion sram; 878 879 struct omap_dma_port_if_s { 880 uint32_t (*read[3])(struct omap_mpu_state_s *s, 881 hwaddr offset); 882 void (*write[3])(struct omap_mpu_state_s *s, 883 hwaddr offset, uint32_t value); 884 int (*addr_valid)(struct omap_mpu_state_s *s, 885 hwaddr addr); 886 } port[__omap_dma_port_last]; 887 888 uint64_t sdram_size; 889 unsigned long sram_size; 890 891 /* MPUI-TIPB peripherals */ 892 struct omap_uart_s *uart[3]; 893 894 DeviceState *gpio; 895 896 struct omap_mcbsp_s *mcbsp1; 897 struct omap_mcbsp_s *mcbsp3; 898 899 /* MPU public TIPB peripherals */ 900 struct omap_32khz_timer_s *os_timer; 901 902 struct omap_mmc_s *mmc; 903 904 struct omap_mpuio_s *mpuio; 905 906 struct omap_uwire_s *microwire; 907 908 struct omap_pwl_s *pwl; 909 struct omap_pwt_s *pwt; 910 DeviceState *i2c[2]; 911 912 struct omap_rtc_s *rtc; 913 914 struct omap_mcbsp_s *mcbsp2; 915 916 struct omap_lpg_s *led[2]; 917 918 /* MPU private TIPB peripherals */ 919 DeviceState *ih[2]; 920 921 struct soc_dma_s *dma; 922 923 struct omap_mpu_timer_s *timer[3]; 924 struct omap_watchdog_timer_s *wdt; 925 926 struct omap_lcd_panel_s *lcd; 927 928 uint32_t ulpd_pm_regs[21]; 929 int64_t ulpd_gauge_start; 930 931 uint32_t func_mux_ctrl[14]; 932 uint32_t comp_mode_ctrl[1]; 933 uint32_t pull_dwn_ctrl[4]; 934 uint32_t gate_inh_ctrl[1]; 935 uint32_t voltage_ctrl[1]; 936 uint32_t test_dbg_ctrl[1]; 937 uint32_t mod_conf_ctrl[1]; 938 int compat1509; 939 940 uint32_t mpui_ctrl; 941 942 struct omap_tipb_bridge_s *private_tipb; 943 struct omap_tipb_bridge_s *public_tipb; 944 945 uint32_t tcmi_regs[17]; 946 947 struct dpll_ctl_s *dpll[3]; 948 949 omap_clk clks; 950 struct { 951 int cold_start; 952 int clocking_scheme; 953 uint16_t arm_ckctl; 954 uint16_t arm_idlect1; 955 uint16_t arm_idlect2; 956 uint16_t arm_ewupct; 957 uint16_t arm_rstct1; 958 uint16_t arm_rstct2; 959 uint16_t arm_ckout1; 960 int dpll1_mode; 961 uint16_t dsp_idlect1; 962 uint16_t dsp_idlect2; 963 uint16_t dsp_rstct2; 964 } clkm; 965 966 /* OMAP2-only peripherals */ 967 struct omap_l4_s *l4; 968 969 struct omap_gp_timer_s *gptimer[12]; 970 struct omap_synctimer_s *synctimer; 971 972 struct omap_prcm_s *prcm; 973 struct omap_sdrc_s *sdrc; 974 struct omap_gpmc_s *gpmc; 975 struct omap_sysctl_s *sysc; 976 977 struct omap_mcspi_s *mcspi[2]; 978 979 struct omap_dss_s *dss; 980 981 struct omap_eac_s *eac; 982 }; 983 984 /* omap1.c */ 985 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 986 const char *core); 987 988 /* omap2.c */ 989 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 990 const char *core); 991 992 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 993 void omap_badwidth_write8(void *opaque, hwaddr addr, 994 uint32_t value); 995 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 996 void omap_badwidth_write16(void *opaque, hwaddr addr, 997 uint32_t value); 998 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 999 void omap_badwidth_write32(void *opaque, hwaddr addr, 1000 uint32_t value); 1001 1002 void omap_mpu_wakeup(void *opaque, int irq, int req); 1003 1004 # define OMAP_BAD_REG(paddr) \ 1005 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1006 __func__, paddr) 1007 # define OMAP_RO_REG(paddr) \ 1008 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 1009 HWADDR_PRIx "\n", \ 1010 __func__, paddr) 1011 1012 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1013 (Board-specifc tags are not here) */ 1014 #define OMAP_TAG_CLOCK 0x4f01 1015 #define OMAP_TAG_MMC 0x4f02 1016 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1017 #define OMAP_TAG_USB 0x4f04 1018 #define OMAP_TAG_LCD 0x4f05 1019 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1020 #define OMAP_TAG_UART 0x4f07 1021 #define OMAP_TAG_FBMEM 0x4f08 1022 #define OMAP_TAG_STI_CONSOLE 0x4f09 1023 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1024 #define OMAP_TAG_PARTITION 0x4f0b 1025 #define OMAP_TAG_TEA5761 0x4f10 1026 #define OMAP_TAG_TMP105 0x4f11 1027 #define OMAP_TAG_BOOT_REASON 0x4f80 1028 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1029 #define OMAP_TAG_VERSION_STR 0x4f82 1030 1031 enum { 1032 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1033 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1034 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1035 }; 1036 1037 #define OMAP_GPIOSW_INVERTED 0x0001 1038 #define OMAP_GPIOSW_OUTPUT 0x0002 1039 1040 # define OMAP_MPUI_REG_MASK 0x000007ff 1041 1042 #endif 1043