1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "hw/input/tsc2xxx.h" 25 #include "target/arm/cpu-qom.h" 26 #include "qemu/log.h" 27 #include "qom/object.h" 28 29 # define OMAP_EMIFS_BASE 0x00000000 30 # define OMAP2_Q0_BASE 0x00000000 31 # define OMAP_CS0_BASE 0x00000000 32 # define OMAP_CS1_BASE 0x04000000 33 # define OMAP_CS2_BASE 0x08000000 34 # define OMAP_CS3_BASE 0x0c000000 35 # define OMAP_EMIFF_BASE 0x10000000 36 # define OMAP_IMIF_BASE 0x20000000 37 # define OMAP_LOCALBUS_BASE 0x30000000 38 # define OMAP2_Q1_BASE 0x40000000 39 # define OMAP2_L4_BASE 0x48000000 40 # define OMAP2_SRAM_BASE 0x40200000 41 # define OMAP2_L3_BASE 0x68000000 42 # define OMAP2_Q2_BASE 0x80000000 43 # define OMAP2_Q3_BASE 0xc0000000 44 # define OMAP_MPUI_BASE 0xe1000000 45 46 # define OMAP730_SRAM_SIZE 0x00032000 47 # define OMAP15XX_SRAM_SIZE 0x00030000 48 # define OMAP16XX_SRAM_SIZE 0x00004000 49 # define OMAP1611_SRAM_SIZE 0x0003e800 50 # define OMAP242X_SRAM_SIZE 0x000a0000 51 # define OMAP243X_SRAM_SIZE 0x00010000 52 # define OMAP_CS0_SIZE 0x04000000 53 # define OMAP_CS1_SIZE 0x04000000 54 # define OMAP_CS2_SIZE 0x04000000 55 # define OMAP_CS3_SIZE 0x04000000 56 57 /* omap_clk.c */ 58 struct omap_mpu_state_s; 59 typedef struct clk *omap_clk; 60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 61 void omap_clk_init(struct omap_mpu_state_s *mpu); 62 void omap_clk_adduser(struct clk *clk, qemu_irq user); 63 void omap_clk_get(omap_clk clk); 64 void omap_clk_put(omap_clk clk); 65 void omap_clk_onoff(omap_clk clk, int on); 66 void omap_clk_canidle(omap_clk clk, int can); 67 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 68 int64_t omap_clk_getrate(omap_clk clk); 69 void omap_clk_reparent(omap_clk clk, omap_clk parent); 70 71 /* omap_intc.c */ 72 #define TYPE_OMAP_INTC "common-omap-intc" 73 typedef struct omap_intr_handler_s omap_intr_handler; 74 DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC, 75 TYPE_OMAP_INTC) 76 77 78 /* 79 * TODO: Ideally we should have a clock framework that 80 * let us wire these clocks up with QOM properties or links. 81 * 82 * qdev should support a generic means of defining a 'port' with 83 * an arbitrary interface for connecting two devices. Then we 84 * could reframe the omap clock API in terms of clock ports, 85 * and get some type safety. For now the best qdev provides is 86 * passing an arbitrary pointer. 87 * (It's not possible to pass in the string which is the clock 88 * name, because this device does not have the necessary information 89 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 90 * translation.) 91 */ 92 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); 93 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); 94 95 /* omap_i2c.c */ 96 #define TYPE_OMAP_I2C "omap_i2c" 97 typedef struct OMAPI2CState OMAPI2CState; 98 DECLARE_INSTANCE_CHECKER(OMAPI2CState, OMAP_I2C, 99 TYPE_OMAP_I2C) 100 101 102 /* TODO: clock framework (see above) */ 103 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 104 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 105 106 /* omap_gpio.c */ 107 #define TYPE_OMAP1_GPIO "omap-gpio" 108 DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO, 109 TYPE_OMAP1_GPIO) 110 111 #define TYPE_OMAP2_GPIO "omap2-gpio" 112 DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO, 113 TYPE_OMAP2_GPIO) 114 115 typedef struct omap_gpif_s omap_gpif; 116 typedef struct omap2_gpif_s omap2_gpif; 117 118 /* TODO: clock framework (see above) */ 119 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk); 120 121 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); 122 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); 123 124 /* OMAP2 l4 Interconnect */ 125 struct omap_l4_s; 126 struct omap_l4_region_s { 127 hwaddr offset; 128 size_t size; 129 int access; 130 }; 131 struct omap_l4_agent_info_s { 132 int ta; 133 int region; 134 int regions; 135 int ta_region; 136 }; 137 struct omap_target_agent_s { 138 MemoryRegion iomem; 139 struct omap_l4_s *bus; 140 int regions; 141 const struct omap_l4_region_s *start; 142 hwaddr base; 143 uint32_t component; 144 uint32_t control; 145 uint32_t status; 146 }; 147 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 148 hwaddr base, int ta_num); 149 150 struct omap_target_agent_s; 151 struct omap_target_agent_s *omap_l4ta_get( 152 struct omap_l4_s *bus, 153 const struct omap_l4_region_s *regions, 154 const struct omap_l4_agent_info_s *agents, 155 int cs); 156 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 157 int region, MemoryRegion *mr); 158 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 159 int region); 160 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 161 int region); 162 163 /* OMAP2 SDRAM controller */ 164 struct omap_sdrc_s; 165 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 166 hwaddr base); 167 void omap_sdrc_reset(struct omap_sdrc_s *s); 168 169 /* OMAP2 general purpose memory controller */ 170 struct omap_gpmc_s; 171 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 172 hwaddr base, 173 qemu_irq irq, qemu_irq drq); 174 void omap_gpmc_reset(struct omap_gpmc_s *s); 175 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 176 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 177 178 /* 179 * Common IRQ numbers for level 1 interrupt handler 180 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 181 */ 182 # define OMAP_INT_CAMERA 1 183 # define OMAP_INT_FIQ 3 184 # define OMAP_INT_RTDX 6 185 # define OMAP_INT_DSP_MMU_ABORT 7 186 # define OMAP_INT_HOST 8 187 # define OMAP_INT_ABORT 9 188 # define OMAP_INT_BRIDGE_PRIV 13 189 # define OMAP_INT_GPIO_BANK1 14 190 # define OMAP_INT_UART3 15 191 # define OMAP_INT_TIMER3 16 192 # define OMAP_INT_DMA_CH0_6 19 193 # define OMAP_INT_DMA_CH1_7 20 194 # define OMAP_INT_DMA_CH2_8 21 195 # define OMAP_INT_DMA_CH3 22 196 # define OMAP_INT_DMA_CH4 23 197 # define OMAP_INT_DMA_CH5 24 198 # define OMAP_INT_DMA_LCD 25 199 # define OMAP_INT_TIMER1 26 200 # define OMAP_INT_WD_TIMER 27 201 # define OMAP_INT_BRIDGE_PUB 28 202 # define OMAP_INT_TIMER2 30 203 # define OMAP_INT_LCD_CTRL 31 204 205 /* 206 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 207 */ 208 # define OMAP_INT_15XX_IH2_IRQ 0 209 # define OMAP_INT_15XX_LB_MMU 17 210 # define OMAP_INT_15XX_LOCAL_BUS 29 211 212 /* 213 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 214 */ 215 # define OMAP_INT_1510_SPI_TX 4 216 # define OMAP_INT_1510_SPI_RX 5 217 # define OMAP_INT_1510_DSP_MAILBOX1 10 218 # define OMAP_INT_1510_DSP_MAILBOX2 11 219 220 /* 221 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 222 */ 223 # define OMAP_INT_310_McBSP2_TX 4 224 # define OMAP_INT_310_McBSP2_RX 5 225 # define OMAP_INT_310_HSB_MAILBOX1 12 226 # define OMAP_INT_310_HSAB_MMU 18 227 228 /* 229 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 230 */ 231 # define OMAP_INT_1610_IH2_IRQ 0 232 # define OMAP_INT_1610_IH2_FIQ 2 233 # define OMAP_INT_1610_McBSP2_TX 4 234 # define OMAP_INT_1610_McBSP2_RX 5 235 # define OMAP_INT_1610_DSP_MAILBOX1 10 236 # define OMAP_INT_1610_DSP_MAILBOX2 11 237 # define OMAP_INT_1610_LCD_LINE 12 238 # define OMAP_INT_1610_GPTIMER1 17 239 # define OMAP_INT_1610_GPTIMER2 18 240 # define OMAP_INT_1610_SSR_FIFO_0 29 241 242 /* 243 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 244 */ 245 # define OMAP_INT_730_IH2_FIQ 0 246 # define OMAP_INT_730_IH2_IRQ 1 247 # define OMAP_INT_730_USB_NON_ISO 2 248 # define OMAP_INT_730_USB_ISO 3 249 # define OMAP_INT_730_ICR 4 250 # define OMAP_INT_730_EAC 5 251 # define OMAP_INT_730_GPIO_BANK1 6 252 # define OMAP_INT_730_GPIO_BANK2 7 253 # define OMAP_INT_730_GPIO_BANK3 8 254 # define OMAP_INT_730_McBSP2TX 10 255 # define OMAP_INT_730_McBSP2RX 11 256 # define OMAP_INT_730_McBSP2RX_OVF 12 257 # define OMAP_INT_730_LCD_LINE 14 258 # define OMAP_INT_730_GSM_PROTECT 15 259 # define OMAP_INT_730_TIMER3 16 260 # define OMAP_INT_730_GPIO_BANK5 17 261 # define OMAP_INT_730_GPIO_BANK6 18 262 # define OMAP_INT_730_SPGIO_WR 29 263 264 /* 265 * Common IRQ numbers for level 2 interrupt handler 266 */ 267 # define OMAP_INT_KEYBOARD 1 268 # define OMAP_INT_uWireTX 2 269 # define OMAP_INT_uWireRX 3 270 # define OMAP_INT_I2C 4 271 # define OMAP_INT_MPUIO 5 272 # define OMAP_INT_USB_HHC_1 6 273 # define OMAP_INT_McBSP3TX 10 274 # define OMAP_INT_McBSP3RX 11 275 # define OMAP_INT_McBSP1TX 12 276 # define OMAP_INT_McBSP1RX 13 277 # define OMAP_INT_UART1 14 278 # define OMAP_INT_UART2 15 279 # define OMAP_INT_USB_W2FC 20 280 # define OMAP_INT_1WIRE 21 281 # define OMAP_INT_OS_TIMER 22 282 # define OMAP_INT_OQN 23 283 # define OMAP_INT_GAUGE_32K 24 284 # define OMAP_INT_RTC_TIMER 25 285 # define OMAP_INT_RTC_ALARM 26 286 # define OMAP_INT_DSP_MMU 28 287 288 /* 289 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 290 */ 291 # define OMAP_INT_1510_BT_MCSI1TX 16 292 # define OMAP_INT_1510_BT_MCSI1RX 17 293 # define OMAP_INT_1510_SoSSI_MATCH 19 294 # define OMAP_INT_1510_MEM_STICK 27 295 # define OMAP_INT_1510_COM_SPI_RO 31 296 297 /* 298 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 299 */ 300 # define OMAP_INT_310_FAC 0 301 # define OMAP_INT_310_USB_HHC_2 7 302 # define OMAP_INT_310_MCSI1_FE 16 303 # define OMAP_INT_310_MCSI2_FE 17 304 # define OMAP_INT_310_USB_W2FC_ISO 29 305 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 306 # define OMAP_INT_310_McBSP2RX_OF 31 307 308 /* 309 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 310 */ 311 # define OMAP_INT_1610_FAC 0 312 # define OMAP_INT_1610_USB_HHC_2 7 313 # define OMAP_INT_1610_USB_OTG 8 314 # define OMAP_INT_1610_SoSSI 9 315 # define OMAP_INT_1610_BT_MCSI1TX 16 316 # define OMAP_INT_1610_BT_MCSI1RX 17 317 # define OMAP_INT_1610_SoSSI_MATCH 19 318 # define OMAP_INT_1610_MEM_STICK 27 319 # define OMAP_INT_1610_McBSP2RX_OF 31 320 # define OMAP_INT_1610_STI 32 321 # define OMAP_INT_1610_STI_WAKEUP 33 322 # define OMAP_INT_1610_GPTIMER3 34 323 # define OMAP_INT_1610_GPTIMER4 35 324 # define OMAP_INT_1610_GPTIMER5 36 325 # define OMAP_INT_1610_GPTIMER6 37 326 # define OMAP_INT_1610_GPTIMER7 38 327 # define OMAP_INT_1610_GPTIMER8 39 328 # define OMAP_INT_1610_GPIO_BANK2 40 329 # define OMAP_INT_1610_GPIO_BANK3 41 330 # define OMAP_INT_1610_MMC2 42 331 # define OMAP_INT_1610_CF 43 332 # define OMAP_INT_1610_WAKE_UP_REQ 46 333 # define OMAP_INT_1610_GPIO_BANK4 48 334 # define OMAP_INT_1610_SPI 49 335 # define OMAP_INT_1610_DMA_CH6 53 336 # define OMAP_INT_1610_DMA_CH7 54 337 # define OMAP_INT_1610_DMA_CH8 55 338 # define OMAP_INT_1610_DMA_CH9 56 339 # define OMAP_INT_1610_DMA_CH10 57 340 # define OMAP_INT_1610_DMA_CH11 58 341 # define OMAP_INT_1610_DMA_CH12 59 342 # define OMAP_INT_1610_DMA_CH13 60 343 # define OMAP_INT_1610_DMA_CH14 61 344 # define OMAP_INT_1610_DMA_CH15 62 345 # define OMAP_INT_1610_NAND 63 346 347 /* 348 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 349 */ 350 # define OMAP_INT_730_HW_ERRORS 0 351 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 352 # define OMAP_INT_730_CFCD 2 353 # define OMAP_INT_730_CFIREQ 3 354 # define OMAP_INT_730_I2C 4 355 # define OMAP_INT_730_PCC 5 356 # define OMAP_INT_730_MPU_EXT_NIRQ 6 357 # define OMAP_INT_730_SPI_100K_1 7 358 # define OMAP_INT_730_SYREN_SPI 8 359 # define OMAP_INT_730_VLYNQ 9 360 # define OMAP_INT_730_GPIO_BANK4 10 361 # define OMAP_INT_730_McBSP1TX 11 362 # define OMAP_INT_730_McBSP1RX 12 363 # define OMAP_INT_730_McBSP1RX_OF 13 364 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 365 # define OMAP_INT_730_UART_MODEM_1 15 366 # define OMAP_INT_730_MCSI 16 367 # define OMAP_INT_730_uWireTX 17 368 # define OMAP_INT_730_uWireRX 18 369 # define OMAP_INT_730_SMC_CD 19 370 # define OMAP_INT_730_SMC_IREQ 20 371 # define OMAP_INT_730_HDQ_1WIRE 21 372 # define OMAP_INT_730_TIMER32K 22 373 # define OMAP_INT_730_MMC_SDIO 23 374 # define OMAP_INT_730_UPLD 24 375 # define OMAP_INT_730_USB_HHC_1 27 376 # define OMAP_INT_730_USB_HHC_2 28 377 # define OMAP_INT_730_USB_GENI 29 378 # define OMAP_INT_730_USB_OTG 30 379 # define OMAP_INT_730_CAMERA_IF 31 380 # define OMAP_INT_730_RNG 32 381 # define OMAP_INT_730_DUAL_MODE_TIMER 33 382 # define OMAP_INT_730_DBB_RF_EN 34 383 # define OMAP_INT_730_MPUIO_KEYPAD 35 384 # define OMAP_INT_730_SHA1_MD5 36 385 # define OMAP_INT_730_SPI_100K_2 37 386 # define OMAP_INT_730_RNG_IDLE 38 387 # define OMAP_INT_730_MPUIO 39 388 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 389 # define OMAP_INT_730_LLPC_OE_FALLING 41 390 # define OMAP_INT_730_LLPC_OE_RISING 42 391 # define OMAP_INT_730_LLPC_VSYNC 43 392 # define OMAP_INT_730_WAKE_UP_REQ 46 393 # define OMAP_INT_730_DMA_CH6 53 394 # define OMAP_INT_730_DMA_CH7 54 395 # define OMAP_INT_730_DMA_CH8 55 396 # define OMAP_INT_730_DMA_CH9 56 397 # define OMAP_INT_730_DMA_CH10 57 398 # define OMAP_INT_730_DMA_CH11 58 399 # define OMAP_INT_730_DMA_CH12 59 400 # define OMAP_INT_730_DMA_CH13 60 401 # define OMAP_INT_730_DMA_CH14 61 402 # define OMAP_INT_730_DMA_CH15 62 403 # define OMAP_INT_730_NAND 63 404 405 /* 406 * OMAP-24xx common IRQ numbers 407 */ 408 # define OMAP_INT_24XX_STI 4 409 # define OMAP_INT_24XX_SYS_NIRQ 7 410 # define OMAP_INT_24XX_L3_IRQ 10 411 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 412 # define OMAP_INT_24XX_SDMA_IRQ0 12 413 # define OMAP_INT_24XX_SDMA_IRQ1 13 414 # define OMAP_INT_24XX_SDMA_IRQ2 14 415 # define OMAP_INT_24XX_SDMA_IRQ3 15 416 # define OMAP_INT_243X_MCBSP2_IRQ 16 417 # define OMAP_INT_243X_MCBSP3_IRQ 17 418 # define OMAP_INT_243X_MCBSP4_IRQ 18 419 # define OMAP_INT_243X_MCBSP5_IRQ 19 420 # define OMAP_INT_24XX_GPMC_IRQ 20 421 # define OMAP_INT_24XX_GUFFAW_IRQ 21 422 # define OMAP_INT_24XX_IVA_IRQ 22 423 # define OMAP_INT_24XX_EAC_IRQ 23 424 # define OMAP_INT_24XX_CAM_IRQ 24 425 # define OMAP_INT_24XX_DSS_IRQ 25 426 # define OMAP_INT_24XX_MAIL_U0_MPU 26 427 # define OMAP_INT_24XX_DSP_UMA 27 428 # define OMAP_INT_24XX_DSP_MMU 28 429 # define OMAP_INT_24XX_GPIO_BANK1 29 430 # define OMAP_INT_24XX_GPIO_BANK2 30 431 # define OMAP_INT_24XX_GPIO_BANK3 31 432 # define OMAP_INT_24XX_GPIO_BANK4 32 433 # define OMAP_INT_243X_GPIO_BANK5 33 434 # define OMAP_INT_24XX_MAIL_U3_MPU 34 435 # define OMAP_INT_24XX_WDT3 35 436 # define OMAP_INT_24XX_WDT4 36 437 # define OMAP_INT_24XX_GPTIMER1 37 438 # define OMAP_INT_24XX_GPTIMER2 38 439 # define OMAP_INT_24XX_GPTIMER3 39 440 # define OMAP_INT_24XX_GPTIMER4 40 441 # define OMAP_INT_24XX_GPTIMER5 41 442 # define OMAP_INT_24XX_GPTIMER6 42 443 # define OMAP_INT_24XX_GPTIMER7 43 444 # define OMAP_INT_24XX_GPTIMER8 44 445 # define OMAP_INT_24XX_GPTIMER9 45 446 # define OMAP_INT_24XX_GPTIMER10 46 447 # define OMAP_INT_24XX_GPTIMER11 47 448 # define OMAP_INT_24XX_GPTIMER12 48 449 # define OMAP_INT_24XX_PKA_IRQ 50 450 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 451 # define OMAP_INT_24XX_RNG_IRQ 52 452 # define OMAP_INT_24XX_MG_IRQ 53 453 # define OMAP_INT_24XX_I2C1_IRQ 56 454 # define OMAP_INT_24XX_I2C2_IRQ 57 455 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 456 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 457 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 458 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 459 # define OMAP_INT_243X_MCBSP1_IRQ 64 460 # define OMAP_INT_24XX_MCSPI1_IRQ 65 461 # define OMAP_INT_24XX_MCSPI2_IRQ 66 462 # define OMAP_INT_24XX_SSI1_IRQ0 67 463 # define OMAP_INT_24XX_SSI1_IRQ1 68 464 # define OMAP_INT_24XX_SSI2_IRQ0 69 465 # define OMAP_INT_24XX_SSI2_IRQ1 70 466 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 467 # define OMAP_INT_24XX_UART1_IRQ 72 468 # define OMAP_INT_24XX_UART2_IRQ 73 469 # define OMAP_INT_24XX_UART3_IRQ 74 470 # define OMAP_INT_24XX_USB_IRQ_GEN 75 471 # define OMAP_INT_24XX_USB_IRQ_NISO 76 472 # define OMAP_INT_24XX_USB_IRQ_ISO 77 473 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 474 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 475 # define OMAP_INT_24XX_USB_IRQ_OTG 80 476 # define OMAP_INT_24XX_VLYNQ_IRQ 81 477 # define OMAP_INT_24XX_MMC_IRQ 83 478 # define OMAP_INT_24XX_MS_IRQ 84 479 # define OMAP_INT_24XX_FAC_IRQ 85 480 # define OMAP_INT_24XX_MCSPI3_IRQ 91 481 # define OMAP_INT_243X_HS_USB_MC 92 482 # define OMAP_INT_243X_HS_USB_DMA 93 483 # define OMAP_INT_243X_CARKIT 94 484 # define OMAP_INT_34XX_GPTIMER12 95 485 486 /* omap_dma.c */ 487 enum omap_dma_model { 488 omap_dma_3_0, 489 omap_dma_3_1, 490 omap_dma_3_2, 491 omap_dma_4, 492 }; 493 494 struct soc_dma_s; 495 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 496 MemoryRegion *sysmem, 497 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 498 enum omap_dma_model model); 499 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 500 MemoryRegion *sysmem, 501 struct omap_mpu_state_s *mpu, int fifo, 502 int chans, omap_clk iclk, omap_clk fclk); 503 void omap_dma_reset(struct soc_dma_s *s); 504 505 struct dma_irq_map { 506 int ih; 507 int intr; 508 }; 509 510 /* Only used in OMAP DMA 3.x gigacells */ 511 enum omap_dma_port { 512 emiff = 0, 513 emifs, 514 imif, /* omap16xx: ocp_t1 */ 515 tipb, 516 local, /* omap16xx: ocp_t2 */ 517 tipb_mpui, 518 __omap_dma_port_last, 519 }; 520 521 typedef enum { 522 constant = 0, 523 post_incremented, 524 single_index, 525 double_index, 526 } omap_dma_addressing_t; 527 528 /* Only used in OMAP DMA 3.x gigacells */ 529 struct omap_dma_lcd_channel_s { 530 enum omap_dma_port src; 531 hwaddr src_f1_top; 532 hwaddr src_f1_bottom; 533 hwaddr src_f2_top; 534 hwaddr src_f2_bottom; 535 536 /* Used in OMAP DMA 3.2 gigacell */ 537 unsigned char brust_f1; 538 unsigned char pack_f1; 539 unsigned char data_type_f1; 540 unsigned char brust_f2; 541 unsigned char pack_f2; 542 unsigned char data_type_f2; 543 unsigned char end_prog; 544 unsigned char repeat; 545 unsigned char auto_init; 546 unsigned char priority; 547 unsigned char fs; 548 unsigned char running; 549 unsigned char bs; 550 unsigned char omap_3_1_compatible_disable; 551 unsigned char dst; 552 unsigned char lch_type; 553 int16_t element_index_f1; 554 int16_t element_index_f2; 555 int32_t frame_index_f1; 556 int32_t frame_index_f2; 557 uint16_t elements_f1; 558 uint16_t frames_f1; 559 uint16_t elements_f2; 560 uint16_t frames_f2; 561 omap_dma_addressing_t mode_f1; 562 omap_dma_addressing_t mode_f2; 563 564 /* Destination port is fixed. */ 565 int interrupts; 566 int condition; 567 int dual; 568 569 int current_frame; 570 hwaddr phys_framebuffer[2]; 571 qemu_irq irq; 572 struct omap_mpu_state_s *mpu; 573 } *omap_dma_get_lcdch(struct soc_dma_s *s); 574 575 /* 576 * DMA request numbers for OMAP1 577 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 578 */ 579 # define OMAP_DMA_NO_DEVICE 0 580 # define OMAP_DMA_MCSI1_TX 1 581 # define OMAP_DMA_MCSI1_RX 2 582 # define OMAP_DMA_I2C_RX 3 583 # define OMAP_DMA_I2C_TX 4 584 # define OMAP_DMA_EXT_NDMA_REQ0 5 585 # define OMAP_DMA_EXT_NDMA_REQ1 6 586 # define OMAP_DMA_UWIRE_TX 7 587 # define OMAP_DMA_MCBSP1_TX 8 588 # define OMAP_DMA_MCBSP1_RX 9 589 # define OMAP_DMA_MCBSP3_TX 10 590 # define OMAP_DMA_MCBSP3_RX 11 591 # define OMAP_DMA_UART1_TX 12 592 # define OMAP_DMA_UART1_RX 13 593 # define OMAP_DMA_UART2_TX 14 594 # define OMAP_DMA_UART2_RX 15 595 # define OMAP_DMA_MCBSP2_TX 16 596 # define OMAP_DMA_MCBSP2_RX 17 597 # define OMAP_DMA_UART3_TX 18 598 # define OMAP_DMA_UART3_RX 19 599 # define OMAP_DMA_CAMERA_IF_RX 20 600 # define OMAP_DMA_MMC_TX 21 601 # define OMAP_DMA_MMC_RX 22 602 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 603 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 604 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 605 # define OMAP_DMA_USB_W2FC_RX0 26 606 # define OMAP_DMA_USB_W2FC_RX1 27 607 # define OMAP_DMA_USB_W2FC_RX2 28 608 # define OMAP_DMA_USB_W2FC_TX0 29 609 # define OMAP_DMA_USB_W2FC_TX1 30 610 # define OMAP_DMA_USB_W2FC_TX2 31 611 612 /* These are only for 1610 */ 613 # define OMAP_DMA_CRYPTO_DES_IN 32 614 # define OMAP_DMA_SPI_TX 33 615 # define OMAP_DMA_SPI_RX 34 616 # define OMAP_DMA_CRYPTO_HASH 35 617 # define OMAP_DMA_CCP_ATTN 36 618 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 619 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 620 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 621 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 622 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 623 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 624 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 625 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 626 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 627 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 628 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 629 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 630 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 631 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 632 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 633 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 634 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 635 # define OMAP_DMA_MMC2_TX 54 636 # define OMAP_DMA_MMC2_RX 55 637 # define OMAP_DMA_CRYPTO_DES_OUT 56 638 639 /* 640 * DMA request numbers for the OMAP2 641 */ 642 # define OMAP24XX_DMA_NO_DEVICE 0 643 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 644 # define OMAP24XX_DMA_EXT_DMAREQ0 2 645 # define OMAP24XX_DMA_EXT_DMAREQ1 3 646 # define OMAP24XX_DMA_GPMC 4 647 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 648 # define OMAP24XX_DMA_DSS 6 649 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 651 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 652 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 653 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 654 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 655 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 656 # define OMAP24XX_DMA_EXT_DMAREQ2 14 657 # define OMAP24XX_DMA_EXT_DMAREQ3 15 658 # define OMAP24XX_DMA_EXT_DMAREQ4 16 659 # define OMAP24XX_DMA_EAC_AC_RD 17 660 # define OMAP24XX_DMA_EAC_AC_WR 18 661 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 662 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 663 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 664 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 665 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 666 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 667 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 668 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 669 # define OMAP24XX_DMA_I2C1_TX 27 670 # define OMAP24XX_DMA_I2C1_RX 28 671 # define OMAP24XX_DMA_I2C2_TX 29 672 # define OMAP24XX_DMA_I2C2_RX 30 673 # define OMAP24XX_DMA_MCBSP1_TX 31 674 # define OMAP24XX_DMA_MCBSP1_RX 32 675 # define OMAP24XX_DMA_MCBSP2_TX 33 676 # define OMAP24XX_DMA_MCBSP2_RX 34 677 # define OMAP24XX_DMA_SPI1_TX0 35 678 # define OMAP24XX_DMA_SPI1_RX0 36 679 # define OMAP24XX_DMA_SPI1_TX1 37 680 # define OMAP24XX_DMA_SPI1_RX1 38 681 # define OMAP24XX_DMA_SPI1_TX2 39 682 # define OMAP24XX_DMA_SPI1_RX2 40 683 # define OMAP24XX_DMA_SPI1_TX3 41 684 # define OMAP24XX_DMA_SPI1_RX3 42 685 # define OMAP24XX_DMA_SPI2_TX0 43 686 # define OMAP24XX_DMA_SPI2_RX0 44 687 # define OMAP24XX_DMA_SPI2_TX1 45 688 # define OMAP24XX_DMA_SPI2_RX1 46 689 690 # define OMAP24XX_DMA_UART1_TX 49 691 # define OMAP24XX_DMA_UART1_RX 50 692 # define OMAP24XX_DMA_UART2_TX 51 693 # define OMAP24XX_DMA_UART2_RX 52 694 # define OMAP24XX_DMA_UART3_TX 53 695 # define OMAP24XX_DMA_UART3_RX 54 696 # define OMAP24XX_DMA_USB_W2FC_TX0 55 697 # define OMAP24XX_DMA_USB_W2FC_RX0 56 698 # define OMAP24XX_DMA_USB_W2FC_TX1 57 699 # define OMAP24XX_DMA_USB_W2FC_RX1 58 700 # define OMAP24XX_DMA_USB_W2FC_TX2 59 701 # define OMAP24XX_DMA_USB_W2FC_RX2 60 702 # define OMAP24XX_DMA_MMC1_TX 61 703 # define OMAP24XX_DMA_MMC1_RX 62 704 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 705 # define OMAP24XX_DMA_EXT_DMAREQ5 64 706 707 /* omap[123].c */ 708 /* OMAP2 gp timer */ 709 struct omap_gp_timer_s; 710 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 711 qemu_irq irq, omap_clk fclk, omap_clk iclk); 712 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 713 714 /* OMAP2 sysctimer */ 715 struct omap_synctimer_s; 716 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 717 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 718 void omap_synctimer_reset(struct omap_synctimer_s *s); 719 720 struct omap_uart_s; 721 struct omap_uart_s *omap_uart_init(hwaddr base, 722 qemu_irq irq, omap_clk fclk, omap_clk iclk, 723 qemu_irq txdma, qemu_irq rxdma, 724 const char *label, Chardev *chr); 725 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 726 struct omap_target_agent_s *ta, 727 qemu_irq irq, omap_clk fclk, omap_clk iclk, 728 qemu_irq txdma, qemu_irq rxdma, 729 const char *label, Chardev *chr); 730 void omap_uart_reset(struct omap_uart_s *s); 731 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 732 733 struct omap_mpuio_s; 734 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 735 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 736 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 737 738 struct omap_uwire_s; 739 void omap_uwire_attach(struct omap_uwire_s *s, 740 uWireSlave *slave, int chipselect); 741 742 /* OMAP2 spi */ 743 struct omap_mcspi_s; 744 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 745 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 746 void omap_mcspi_attach(struct omap_mcspi_s *s, 747 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 748 int chipselect); 749 void omap_mcspi_reset(struct omap_mcspi_s *s); 750 751 struct I2SCodec { 752 void *opaque; 753 754 /* The CPU can call this if it is generating the clock signal on the 755 * i2s port. The CODEC can ignore it if it is set up as a clock 756 * master and generates its own clock. */ 757 void (*set_rate)(void *opaque, int in, int out); 758 759 void (*tx_swallow)(void *opaque); 760 qemu_irq rx_swallow; 761 qemu_irq tx_start; 762 763 int tx_rate; 764 int cts; 765 int rx_rate; 766 int rts; 767 768 struct i2s_fifo_s { 769 uint8_t *fifo; 770 int len; 771 int start; 772 int size; 773 } in, out; 774 }; 775 struct omap_mcbsp_s; 776 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 777 778 void omap_tap_init(struct omap_target_agent_s *ta, 779 struct omap_mpu_state_s *mpu); 780 781 /* omap_lcdc.c */ 782 struct omap_lcd_panel_s; 783 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 784 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 785 hwaddr base, 786 qemu_irq irq, 787 struct omap_dma_lcd_channel_s *dma, 788 omap_clk clk); 789 790 /* omap_dss.c */ 791 struct rfbi_chip_s { 792 void *opaque; 793 void (*write)(void *opaque, int dc, uint16_t value); 794 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 795 uint16_t (*read)(void *opaque, int dc); 796 }; 797 struct omap_dss_s; 798 void omap_dss_reset(struct omap_dss_s *s); 799 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 800 MemoryRegion *sysmem, 801 hwaddr l3_base, 802 qemu_irq irq, qemu_irq drq, 803 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 804 omap_clk ick1, omap_clk ick2); 805 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 806 807 /* omap_mmc.c */ 808 struct omap_mmc_s; 809 struct omap_mmc_s *omap_mmc_init(hwaddr base, 810 MemoryRegion *sysmem, 811 BlockBackend *blk, 812 qemu_irq irq, qemu_irq dma[], omap_clk clk); 813 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 814 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 815 omap_clk fclk, omap_clk iclk); 816 void omap_mmc_reset(struct omap_mmc_s *s); 817 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 818 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 819 820 /* omap_i2c.c */ 821 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 822 823 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 824 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 825 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 826 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 827 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 828 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 829 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 830 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 831 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 832 833 # define cpu_is_omap15xx(cpu) \ 834 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 835 # define cpu_is_omap16xx(cpu) \ 836 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 837 # define cpu_is_omap24xx(cpu) \ 838 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 839 840 # define cpu_class_omap1(cpu) \ 841 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 842 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 843 # define cpu_class_omap3(cpu) \ 844 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 845 846 struct omap_mpu_state_s { 847 enum omap_mpu_model { 848 omap310, 849 omap1510, 850 omap1610, 851 omap1710, 852 omap2410, 853 omap2420, 854 omap2422, 855 omap2423, 856 omap2430, 857 omap3430, 858 omap3630, 859 } mpu_model; 860 861 ARMCPU *cpu; 862 863 qemu_irq *drq; 864 865 qemu_irq wakeup; 866 867 MemoryRegion ulpd_pm_iomem; 868 MemoryRegion pin_cfg_iomem; 869 MemoryRegion id_iomem; 870 MemoryRegion id_iomem_e18; 871 MemoryRegion id_iomem_ed4; 872 MemoryRegion id_iomem_e20; 873 MemoryRegion mpui_iomem; 874 MemoryRegion tcmi_iomem; 875 MemoryRegion clkm_iomem; 876 MemoryRegion clkdsp_iomem; 877 MemoryRegion mpui_io_iomem; 878 MemoryRegion tap_iomem; 879 MemoryRegion imif_ram; 880 MemoryRegion sram; 881 882 struct omap_dma_port_if_s { 883 uint32_t (*read[3])(struct omap_mpu_state_s *s, 884 hwaddr offset); 885 void (*write[3])(struct omap_mpu_state_s *s, 886 hwaddr offset, uint32_t value); 887 int (*addr_valid)(struct omap_mpu_state_s *s, 888 hwaddr addr); 889 } port[__omap_dma_port_last]; 890 891 uint64_t sdram_size; 892 unsigned long sram_size; 893 894 /* MPUI-TIPB peripherals */ 895 struct omap_uart_s *uart[3]; 896 897 DeviceState *gpio; 898 899 struct omap_mcbsp_s *mcbsp1; 900 struct omap_mcbsp_s *mcbsp3; 901 902 /* MPU public TIPB peripherals */ 903 struct omap_32khz_timer_s *os_timer; 904 905 struct omap_mmc_s *mmc; 906 907 struct omap_mpuio_s *mpuio; 908 909 struct omap_uwire_s *microwire; 910 911 struct omap_pwl_s *pwl; 912 struct omap_pwt_s *pwt; 913 DeviceState *i2c[2]; 914 915 struct omap_rtc_s *rtc; 916 917 struct omap_mcbsp_s *mcbsp2; 918 919 struct omap_lpg_s *led[2]; 920 921 /* MPU private TIPB peripherals */ 922 DeviceState *ih[2]; 923 924 struct soc_dma_s *dma; 925 926 struct omap_mpu_timer_s *timer[3]; 927 struct omap_watchdog_timer_s *wdt; 928 929 struct omap_lcd_panel_s *lcd; 930 931 uint32_t ulpd_pm_regs[21]; 932 int64_t ulpd_gauge_start; 933 934 uint32_t func_mux_ctrl[14]; 935 uint32_t comp_mode_ctrl[1]; 936 uint32_t pull_dwn_ctrl[4]; 937 uint32_t gate_inh_ctrl[1]; 938 uint32_t voltage_ctrl[1]; 939 uint32_t test_dbg_ctrl[1]; 940 uint32_t mod_conf_ctrl[1]; 941 int compat1509; 942 943 uint32_t mpui_ctrl; 944 945 struct omap_tipb_bridge_s *private_tipb; 946 struct omap_tipb_bridge_s *public_tipb; 947 948 uint32_t tcmi_regs[17]; 949 950 struct dpll_ctl_s *dpll[3]; 951 952 omap_clk clks; 953 struct { 954 int cold_start; 955 int clocking_scheme; 956 uint16_t arm_ckctl; 957 uint16_t arm_idlect1; 958 uint16_t arm_idlect2; 959 uint16_t arm_ewupct; 960 uint16_t arm_rstct1; 961 uint16_t arm_rstct2; 962 uint16_t arm_ckout1; 963 int dpll1_mode; 964 uint16_t dsp_idlect1; 965 uint16_t dsp_idlect2; 966 uint16_t dsp_rstct2; 967 } clkm; 968 969 /* OMAP2-only peripherals */ 970 struct omap_l4_s *l4; 971 972 struct omap_gp_timer_s *gptimer[12]; 973 struct omap_synctimer_s *synctimer; 974 975 struct omap_prcm_s *prcm; 976 struct omap_sdrc_s *sdrc; 977 struct omap_gpmc_s *gpmc; 978 struct omap_sysctl_s *sysc; 979 980 struct omap_mcspi_s *mcspi[2]; 981 982 struct omap_dss_s *dss; 983 984 struct omap_eac_s *eac; 985 }; 986 987 /* omap1.c */ 988 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 989 const char *core); 990 991 /* omap2.c */ 992 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 993 const char *core); 994 995 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 996 void omap_badwidth_write8(void *opaque, hwaddr addr, 997 uint32_t value); 998 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 999 void omap_badwidth_write16(void *opaque, hwaddr addr, 1000 uint32_t value); 1001 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 1002 void omap_badwidth_write32(void *opaque, hwaddr addr, 1003 uint32_t value); 1004 1005 void omap_mpu_wakeup(void *opaque, int irq, int req); 1006 1007 # define OMAP_BAD_REG(paddr) \ 1008 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1009 __func__, paddr) 1010 # define OMAP_RO_REG(paddr) \ 1011 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 1012 HWADDR_PRIx "\n", \ 1013 __func__, paddr) 1014 1015 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1016 (Board-specifc tags are not here) */ 1017 #define OMAP_TAG_CLOCK 0x4f01 1018 #define OMAP_TAG_MMC 0x4f02 1019 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1020 #define OMAP_TAG_USB 0x4f04 1021 #define OMAP_TAG_LCD 0x4f05 1022 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1023 #define OMAP_TAG_UART 0x4f07 1024 #define OMAP_TAG_FBMEM 0x4f08 1025 #define OMAP_TAG_STI_CONSOLE 0x4f09 1026 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1027 #define OMAP_TAG_PARTITION 0x4f0b 1028 #define OMAP_TAG_TEA5761 0x4f10 1029 #define OMAP_TAG_TMP105 0x4f11 1030 #define OMAP_TAG_BOOT_REASON 0x4f80 1031 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1032 #define OMAP_TAG_VERSION_STR 0x4f82 1033 1034 enum { 1035 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1036 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1037 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1038 }; 1039 1040 #define OMAP_GPIOSW_INVERTED 0x0001 1041 #define OMAP_GPIOSW_OUTPUT 0x0002 1042 1043 # define OMAP_MPUI_REG_MASK 0x000007ff 1044 1045 #endif 1046