1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef hw_omap_h 20 #include "exec/memory.h" 21 # define hw_omap_h "omap.h" 22 #include "hw/irq.h" 23 #include "hw/input/tsc2xxx.h" 24 #include "target/arm/cpu-qom.h" 25 #include "qemu/log.h" 26 27 # define OMAP_EMIFS_BASE 0x00000000 28 # define OMAP2_Q0_BASE 0x00000000 29 # define OMAP_CS0_BASE 0x00000000 30 # define OMAP_CS1_BASE 0x04000000 31 # define OMAP_CS2_BASE 0x08000000 32 # define OMAP_CS3_BASE 0x0c000000 33 # define OMAP_EMIFF_BASE 0x10000000 34 # define OMAP_IMIF_BASE 0x20000000 35 # define OMAP_LOCALBUS_BASE 0x30000000 36 # define OMAP2_Q1_BASE 0x40000000 37 # define OMAP2_L4_BASE 0x48000000 38 # define OMAP2_SRAM_BASE 0x40200000 39 # define OMAP2_L3_BASE 0x68000000 40 # define OMAP2_Q2_BASE 0x80000000 41 # define OMAP2_Q3_BASE 0xc0000000 42 # define OMAP_MPUI_BASE 0xe1000000 43 44 # define OMAP730_SRAM_SIZE 0x00032000 45 # define OMAP15XX_SRAM_SIZE 0x00030000 46 # define OMAP16XX_SRAM_SIZE 0x00004000 47 # define OMAP1611_SRAM_SIZE 0x0003e800 48 # define OMAP242X_SRAM_SIZE 0x000a0000 49 # define OMAP243X_SRAM_SIZE 0x00010000 50 # define OMAP_CS0_SIZE 0x04000000 51 # define OMAP_CS1_SIZE 0x04000000 52 # define OMAP_CS2_SIZE 0x04000000 53 # define OMAP_CS3_SIZE 0x04000000 54 55 /* omap_clk.c */ 56 struct omap_mpu_state_s; 57 typedef struct clk *omap_clk; 58 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 59 void omap_clk_init(struct omap_mpu_state_s *mpu); 60 void omap_clk_adduser(struct clk *clk, qemu_irq user); 61 void omap_clk_get(omap_clk clk); 62 void omap_clk_put(omap_clk clk); 63 void omap_clk_onoff(omap_clk clk, int on); 64 void omap_clk_canidle(omap_clk clk, int can); 65 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 66 int64_t omap_clk_getrate(omap_clk clk); 67 void omap_clk_reparent(omap_clk clk, omap_clk parent); 68 69 /* OMAP2 l4 Interconnect */ 70 struct omap_l4_s; 71 struct omap_l4_region_s { 72 hwaddr offset; 73 size_t size; 74 int access; 75 }; 76 struct omap_l4_agent_info_s { 77 int ta; 78 int region; 79 int regions; 80 int ta_region; 81 }; 82 struct omap_target_agent_s { 83 MemoryRegion iomem; 84 struct omap_l4_s *bus; 85 int regions; 86 const struct omap_l4_region_s *start; 87 hwaddr base; 88 uint32_t component; 89 uint32_t control; 90 uint32_t status; 91 }; 92 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 93 hwaddr base, int ta_num); 94 95 struct omap_target_agent_s; 96 struct omap_target_agent_s *omap_l4ta_get( 97 struct omap_l4_s *bus, 98 const struct omap_l4_region_s *regions, 99 const struct omap_l4_agent_info_s *agents, 100 int cs); 101 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 102 int region, MemoryRegion *mr); 103 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 104 int region); 105 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 106 int region); 107 108 /* OMAP2 SDRAM controller */ 109 struct omap_sdrc_s; 110 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 111 hwaddr base); 112 void omap_sdrc_reset(struct omap_sdrc_s *s); 113 114 /* OMAP2 general purpose memory controller */ 115 struct omap_gpmc_s; 116 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 117 hwaddr base, 118 qemu_irq irq, qemu_irq drq); 119 void omap_gpmc_reset(struct omap_gpmc_s *s); 120 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 121 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 122 123 /* 124 * Common IRQ numbers for level 1 interrupt handler 125 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 126 */ 127 # define OMAP_INT_CAMERA 1 128 # define OMAP_INT_FIQ 3 129 # define OMAP_INT_RTDX 6 130 # define OMAP_INT_DSP_MMU_ABORT 7 131 # define OMAP_INT_HOST 8 132 # define OMAP_INT_ABORT 9 133 # define OMAP_INT_BRIDGE_PRIV 13 134 # define OMAP_INT_GPIO_BANK1 14 135 # define OMAP_INT_UART3 15 136 # define OMAP_INT_TIMER3 16 137 # define OMAP_INT_DMA_CH0_6 19 138 # define OMAP_INT_DMA_CH1_7 20 139 # define OMAP_INT_DMA_CH2_8 21 140 # define OMAP_INT_DMA_CH3 22 141 # define OMAP_INT_DMA_CH4 23 142 # define OMAP_INT_DMA_CH5 24 143 # define OMAP_INT_DMA_LCD 25 144 # define OMAP_INT_TIMER1 26 145 # define OMAP_INT_WD_TIMER 27 146 # define OMAP_INT_BRIDGE_PUB 28 147 # define OMAP_INT_TIMER2 30 148 # define OMAP_INT_LCD_CTRL 31 149 150 /* 151 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 152 */ 153 # define OMAP_INT_15XX_IH2_IRQ 0 154 # define OMAP_INT_15XX_LB_MMU 17 155 # define OMAP_INT_15XX_LOCAL_BUS 29 156 157 /* 158 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 159 */ 160 # define OMAP_INT_1510_SPI_TX 4 161 # define OMAP_INT_1510_SPI_RX 5 162 # define OMAP_INT_1510_DSP_MAILBOX1 10 163 # define OMAP_INT_1510_DSP_MAILBOX2 11 164 165 /* 166 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 167 */ 168 # define OMAP_INT_310_McBSP2_TX 4 169 # define OMAP_INT_310_McBSP2_RX 5 170 # define OMAP_INT_310_HSB_MAILBOX1 12 171 # define OMAP_INT_310_HSAB_MMU 18 172 173 /* 174 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 175 */ 176 # define OMAP_INT_1610_IH2_IRQ 0 177 # define OMAP_INT_1610_IH2_FIQ 2 178 # define OMAP_INT_1610_McBSP2_TX 4 179 # define OMAP_INT_1610_McBSP2_RX 5 180 # define OMAP_INT_1610_DSP_MAILBOX1 10 181 # define OMAP_INT_1610_DSP_MAILBOX2 11 182 # define OMAP_INT_1610_LCD_LINE 12 183 # define OMAP_INT_1610_GPTIMER1 17 184 # define OMAP_INT_1610_GPTIMER2 18 185 # define OMAP_INT_1610_SSR_FIFO_0 29 186 187 /* 188 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 189 */ 190 # define OMAP_INT_730_IH2_FIQ 0 191 # define OMAP_INT_730_IH2_IRQ 1 192 # define OMAP_INT_730_USB_NON_ISO 2 193 # define OMAP_INT_730_USB_ISO 3 194 # define OMAP_INT_730_ICR 4 195 # define OMAP_INT_730_EAC 5 196 # define OMAP_INT_730_GPIO_BANK1 6 197 # define OMAP_INT_730_GPIO_BANK2 7 198 # define OMAP_INT_730_GPIO_BANK3 8 199 # define OMAP_INT_730_McBSP2TX 10 200 # define OMAP_INT_730_McBSP2RX 11 201 # define OMAP_INT_730_McBSP2RX_OVF 12 202 # define OMAP_INT_730_LCD_LINE 14 203 # define OMAP_INT_730_GSM_PROTECT 15 204 # define OMAP_INT_730_TIMER3 16 205 # define OMAP_INT_730_GPIO_BANK5 17 206 # define OMAP_INT_730_GPIO_BANK6 18 207 # define OMAP_INT_730_SPGIO_WR 29 208 209 /* 210 * Common IRQ numbers for level 2 interrupt handler 211 */ 212 # define OMAP_INT_KEYBOARD 1 213 # define OMAP_INT_uWireTX 2 214 # define OMAP_INT_uWireRX 3 215 # define OMAP_INT_I2C 4 216 # define OMAP_INT_MPUIO 5 217 # define OMAP_INT_USB_HHC_1 6 218 # define OMAP_INT_McBSP3TX 10 219 # define OMAP_INT_McBSP3RX 11 220 # define OMAP_INT_McBSP1TX 12 221 # define OMAP_INT_McBSP1RX 13 222 # define OMAP_INT_UART1 14 223 # define OMAP_INT_UART2 15 224 # define OMAP_INT_USB_W2FC 20 225 # define OMAP_INT_1WIRE 21 226 # define OMAP_INT_OS_TIMER 22 227 # define OMAP_INT_OQN 23 228 # define OMAP_INT_GAUGE_32K 24 229 # define OMAP_INT_RTC_TIMER 25 230 # define OMAP_INT_RTC_ALARM 26 231 # define OMAP_INT_DSP_MMU 28 232 233 /* 234 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 235 */ 236 # define OMAP_INT_1510_BT_MCSI1TX 16 237 # define OMAP_INT_1510_BT_MCSI1RX 17 238 # define OMAP_INT_1510_SoSSI_MATCH 19 239 # define OMAP_INT_1510_MEM_STICK 27 240 # define OMAP_INT_1510_COM_SPI_RO 31 241 242 /* 243 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 244 */ 245 # define OMAP_INT_310_FAC 0 246 # define OMAP_INT_310_USB_HHC_2 7 247 # define OMAP_INT_310_MCSI1_FE 16 248 # define OMAP_INT_310_MCSI2_FE 17 249 # define OMAP_INT_310_USB_W2FC_ISO 29 250 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 251 # define OMAP_INT_310_McBSP2RX_OF 31 252 253 /* 254 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 255 */ 256 # define OMAP_INT_1610_FAC 0 257 # define OMAP_INT_1610_USB_HHC_2 7 258 # define OMAP_INT_1610_USB_OTG 8 259 # define OMAP_INT_1610_SoSSI 9 260 # define OMAP_INT_1610_BT_MCSI1TX 16 261 # define OMAP_INT_1610_BT_MCSI1RX 17 262 # define OMAP_INT_1610_SoSSI_MATCH 19 263 # define OMAP_INT_1610_MEM_STICK 27 264 # define OMAP_INT_1610_McBSP2RX_OF 31 265 # define OMAP_INT_1610_STI 32 266 # define OMAP_INT_1610_STI_WAKEUP 33 267 # define OMAP_INT_1610_GPTIMER3 34 268 # define OMAP_INT_1610_GPTIMER4 35 269 # define OMAP_INT_1610_GPTIMER5 36 270 # define OMAP_INT_1610_GPTIMER6 37 271 # define OMAP_INT_1610_GPTIMER7 38 272 # define OMAP_INT_1610_GPTIMER8 39 273 # define OMAP_INT_1610_GPIO_BANK2 40 274 # define OMAP_INT_1610_GPIO_BANK3 41 275 # define OMAP_INT_1610_MMC2 42 276 # define OMAP_INT_1610_CF 43 277 # define OMAP_INT_1610_WAKE_UP_REQ 46 278 # define OMAP_INT_1610_GPIO_BANK4 48 279 # define OMAP_INT_1610_SPI 49 280 # define OMAP_INT_1610_DMA_CH6 53 281 # define OMAP_INT_1610_DMA_CH7 54 282 # define OMAP_INT_1610_DMA_CH8 55 283 # define OMAP_INT_1610_DMA_CH9 56 284 # define OMAP_INT_1610_DMA_CH10 57 285 # define OMAP_INT_1610_DMA_CH11 58 286 # define OMAP_INT_1610_DMA_CH12 59 287 # define OMAP_INT_1610_DMA_CH13 60 288 # define OMAP_INT_1610_DMA_CH14 61 289 # define OMAP_INT_1610_DMA_CH15 62 290 # define OMAP_INT_1610_NAND 63 291 292 /* 293 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 294 */ 295 # define OMAP_INT_730_HW_ERRORS 0 296 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 297 # define OMAP_INT_730_CFCD 2 298 # define OMAP_INT_730_CFIREQ 3 299 # define OMAP_INT_730_I2C 4 300 # define OMAP_INT_730_PCC 5 301 # define OMAP_INT_730_MPU_EXT_NIRQ 6 302 # define OMAP_INT_730_SPI_100K_1 7 303 # define OMAP_INT_730_SYREN_SPI 8 304 # define OMAP_INT_730_VLYNQ 9 305 # define OMAP_INT_730_GPIO_BANK4 10 306 # define OMAP_INT_730_McBSP1TX 11 307 # define OMAP_INT_730_McBSP1RX 12 308 # define OMAP_INT_730_McBSP1RX_OF 13 309 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 310 # define OMAP_INT_730_UART_MODEM_1 15 311 # define OMAP_INT_730_MCSI 16 312 # define OMAP_INT_730_uWireTX 17 313 # define OMAP_INT_730_uWireRX 18 314 # define OMAP_INT_730_SMC_CD 19 315 # define OMAP_INT_730_SMC_IREQ 20 316 # define OMAP_INT_730_HDQ_1WIRE 21 317 # define OMAP_INT_730_TIMER32K 22 318 # define OMAP_INT_730_MMC_SDIO 23 319 # define OMAP_INT_730_UPLD 24 320 # define OMAP_INT_730_USB_HHC_1 27 321 # define OMAP_INT_730_USB_HHC_2 28 322 # define OMAP_INT_730_USB_GENI 29 323 # define OMAP_INT_730_USB_OTG 30 324 # define OMAP_INT_730_CAMERA_IF 31 325 # define OMAP_INT_730_RNG 32 326 # define OMAP_INT_730_DUAL_MODE_TIMER 33 327 # define OMAP_INT_730_DBB_RF_EN 34 328 # define OMAP_INT_730_MPUIO_KEYPAD 35 329 # define OMAP_INT_730_SHA1_MD5 36 330 # define OMAP_INT_730_SPI_100K_2 37 331 # define OMAP_INT_730_RNG_IDLE 38 332 # define OMAP_INT_730_MPUIO 39 333 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 334 # define OMAP_INT_730_LLPC_OE_FALLING 41 335 # define OMAP_INT_730_LLPC_OE_RISING 42 336 # define OMAP_INT_730_LLPC_VSYNC 43 337 # define OMAP_INT_730_WAKE_UP_REQ 46 338 # define OMAP_INT_730_DMA_CH6 53 339 # define OMAP_INT_730_DMA_CH7 54 340 # define OMAP_INT_730_DMA_CH8 55 341 # define OMAP_INT_730_DMA_CH9 56 342 # define OMAP_INT_730_DMA_CH10 57 343 # define OMAP_INT_730_DMA_CH11 58 344 # define OMAP_INT_730_DMA_CH12 59 345 # define OMAP_INT_730_DMA_CH13 60 346 # define OMAP_INT_730_DMA_CH14 61 347 # define OMAP_INT_730_DMA_CH15 62 348 # define OMAP_INT_730_NAND 63 349 350 /* 351 * OMAP-24xx common IRQ numbers 352 */ 353 # define OMAP_INT_24XX_STI 4 354 # define OMAP_INT_24XX_SYS_NIRQ 7 355 # define OMAP_INT_24XX_L3_IRQ 10 356 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 357 # define OMAP_INT_24XX_SDMA_IRQ0 12 358 # define OMAP_INT_24XX_SDMA_IRQ1 13 359 # define OMAP_INT_24XX_SDMA_IRQ2 14 360 # define OMAP_INT_24XX_SDMA_IRQ3 15 361 # define OMAP_INT_243X_MCBSP2_IRQ 16 362 # define OMAP_INT_243X_MCBSP3_IRQ 17 363 # define OMAP_INT_243X_MCBSP4_IRQ 18 364 # define OMAP_INT_243X_MCBSP5_IRQ 19 365 # define OMAP_INT_24XX_GPMC_IRQ 20 366 # define OMAP_INT_24XX_GUFFAW_IRQ 21 367 # define OMAP_INT_24XX_IVA_IRQ 22 368 # define OMAP_INT_24XX_EAC_IRQ 23 369 # define OMAP_INT_24XX_CAM_IRQ 24 370 # define OMAP_INT_24XX_DSS_IRQ 25 371 # define OMAP_INT_24XX_MAIL_U0_MPU 26 372 # define OMAP_INT_24XX_DSP_UMA 27 373 # define OMAP_INT_24XX_DSP_MMU 28 374 # define OMAP_INT_24XX_GPIO_BANK1 29 375 # define OMAP_INT_24XX_GPIO_BANK2 30 376 # define OMAP_INT_24XX_GPIO_BANK3 31 377 # define OMAP_INT_24XX_GPIO_BANK4 32 378 # define OMAP_INT_243X_GPIO_BANK5 33 379 # define OMAP_INT_24XX_MAIL_U3_MPU 34 380 # define OMAP_INT_24XX_WDT3 35 381 # define OMAP_INT_24XX_WDT4 36 382 # define OMAP_INT_24XX_GPTIMER1 37 383 # define OMAP_INT_24XX_GPTIMER2 38 384 # define OMAP_INT_24XX_GPTIMER3 39 385 # define OMAP_INT_24XX_GPTIMER4 40 386 # define OMAP_INT_24XX_GPTIMER5 41 387 # define OMAP_INT_24XX_GPTIMER6 42 388 # define OMAP_INT_24XX_GPTIMER7 43 389 # define OMAP_INT_24XX_GPTIMER8 44 390 # define OMAP_INT_24XX_GPTIMER9 45 391 # define OMAP_INT_24XX_GPTIMER10 46 392 # define OMAP_INT_24XX_GPTIMER11 47 393 # define OMAP_INT_24XX_GPTIMER12 48 394 # define OMAP_INT_24XX_PKA_IRQ 50 395 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 396 # define OMAP_INT_24XX_RNG_IRQ 52 397 # define OMAP_INT_24XX_MG_IRQ 53 398 # define OMAP_INT_24XX_I2C1_IRQ 56 399 # define OMAP_INT_24XX_I2C2_IRQ 57 400 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 401 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 402 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 403 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 404 # define OMAP_INT_243X_MCBSP1_IRQ 64 405 # define OMAP_INT_24XX_MCSPI1_IRQ 65 406 # define OMAP_INT_24XX_MCSPI2_IRQ 66 407 # define OMAP_INT_24XX_SSI1_IRQ0 67 408 # define OMAP_INT_24XX_SSI1_IRQ1 68 409 # define OMAP_INT_24XX_SSI2_IRQ0 69 410 # define OMAP_INT_24XX_SSI2_IRQ1 70 411 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 412 # define OMAP_INT_24XX_UART1_IRQ 72 413 # define OMAP_INT_24XX_UART2_IRQ 73 414 # define OMAP_INT_24XX_UART3_IRQ 74 415 # define OMAP_INT_24XX_USB_IRQ_GEN 75 416 # define OMAP_INT_24XX_USB_IRQ_NISO 76 417 # define OMAP_INT_24XX_USB_IRQ_ISO 77 418 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 419 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 420 # define OMAP_INT_24XX_USB_IRQ_OTG 80 421 # define OMAP_INT_24XX_VLYNQ_IRQ 81 422 # define OMAP_INT_24XX_MMC_IRQ 83 423 # define OMAP_INT_24XX_MS_IRQ 84 424 # define OMAP_INT_24XX_FAC_IRQ 85 425 # define OMAP_INT_24XX_MCSPI3_IRQ 91 426 # define OMAP_INT_243X_HS_USB_MC 92 427 # define OMAP_INT_243X_HS_USB_DMA 93 428 # define OMAP_INT_243X_CARKIT 94 429 # define OMAP_INT_34XX_GPTIMER12 95 430 431 /* omap_dma.c */ 432 enum omap_dma_model { 433 omap_dma_3_0, 434 omap_dma_3_1, 435 omap_dma_3_2, 436 omap_dma_4, 437 }; 438 439 struct soc_dma_s; 440 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 441 MemoryRegion *sysmem, 442 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 443 enum omap_dma_model model); 444 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 445 MemoryRegion *sysmem, 446 struct omap_mpu_state_s *mpu, int fifo, 447 int chans, omap_clk iclk, omap_clk fclk); 448 void omap_dma_reset(struct soc_dma_s *s); 449 450 struct dma_irq_map { 451 int ih; 452 int intr; 453 }; 454 455 /* Only used in OMAP DMA 3.x gigacells */ 456 enum omap_dma_port { 457 emiff = 0, 458 emifs, 459 imif, /* omap16xx: ocp_t1 */ 460 tipb, 461 local, /* omap16xx: ocp_t2 */ 462 tipb_mpui, 463 __omap_dma_port_last, 464 }; 465 466 typedef enum { 467 constant = 0, 468 post_incremented, 469 single_index, 470 double_index, 471 } omap_dma_addressing_t; 472 473 /* Only used in OMAP DMA 3.x gigacells */ 474 struct omap_dma_lcd_channel_s { 475 enum omap_dma_port src; 476 hwaddr src_f1_top; 477 hwaddr src_f1_bottom; 478 hwaddr src_f2_top; 479 hwaddr src_f2_bottom; 480 481 /* Used in OMAP DMA 3.2 gigacell */ 482 unsigned char brust_f1; 483 unsigned char pack_f1; 484 unsigned char data_type_f1; 485 unsigned char brust_f2; 486 unsigned char pack_f2; 487 unsigned char data_type_f2; 488 unsigned char end_prog; 489 unsigned char repeat; 490 unsigned char auto_init; 491 unsigned char priority; 492 unsigned char fs; 493 unsigned char running; 494 unsigned char bs; 495 unsigned char omap_3_1_compatible_disable; 496 unsigned char dst; 497 unsigned char lch_type; 498 int16_t element_index_f1; 499 int16_t element_index_f2; 500 int32_t frame_index_f1; 501 int32_t frame_index_f2; 502 uint16_t elements_f1; 503 uint16_t frames_f1; 504 uint16_t elements_f2; 505 uint16_t frames_f2; 506 omap_dma_addressing_t mode_f1; 507 omap_dma_addressing_t mode_f2; 508 509 /* Destination port is fixed. */ 510 int interrupts; 511 int condition; 512 int dual; 513 514 int current_frame; 515 hwaddr phys_framebuffer[2]; 516 qemu_irq irq; 517 struct omap_mpu_state_s *mpu; 518 } *omap_dma_get_lcdch(struct soc_dma_s *s); 519 520 /* 521 * DMA request numbers for OMAP1 522 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 523 */ 524 # define OMAP_DMA_NO_DEVICE 0 525 # define OMAP_DMA_MCSI1_TX 1 526 # define OMAP_DMA_MCSI1_RX 2 527 # define OMAP_DMA_I2C_RX 3 528 # define OMAP_DMA_I2C_TX 4 529 # define OMAP_DMA_EXT_NDMA_REQ0 5 530 # define OMAP_DMA_EXT_NDMA_REQ1 6 531 # define OMAP_DMA_UWIRE_TX 7 532 # define OMAP_DMA_MCBSP1_TX 8 533 # define OMAP_DMA_MCBSP1_RX 9 534 # define OMAP_DMA_MCBSP3_TX 10 535 # define OMAP_DMA_MCBSP3_RX 11 536 # define OMAP_DMA_UART1_TX 12 537 # define OMAP_DMA_UART1_RX 13 538 # define OMAP_DMA_UART2_TX 14 539 # define OMAP_DMA_UART2_RX 15 540 # define OMAP_DMA_MCBSP2_TX 16 541 # define OMAP_DMA_MCBSP2_RX 17 542 # define OMAP_DMA_UART3_TX 18 543 # define OMAP_DMA_UART3_RX 19 544 # define OMAP_DMA_CAMERA_IF_RX 20 545 # define OMAP_DMA_MMC_TX 21 546 # define OMAP_DMA_MMC_RX 22 547 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 548 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 549 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 550 # define OMAP_DMA_USB_W2FC_RX0 26 551 # define OMAP_DMA_USB_W2FC_RX1 27 552 # define OMAP_DMA_USB_W2FC_RX2 28 553 # define OMAP_DMA_USB_W2FC_TX0 29 554 # define OMAP_DMA_USB_W2FC_TX1 30 555 # define OMAP_DMA_USB_W2FC_TX2 31 556 557 /* These are only for 1610 */ 558 # define OMAP_DMA_CRYPTO_DES_IN 32 559 # define OMAP_DMA_SPI_TX 33 560 # define OMAP_DMA_SPI_RX 34 561 # define OMAP_DMA_CRYPTO_HASH 35 562 # define OMAP_DMA_CCP_ATTN 36 563 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 564 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 565 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 566 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 567 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 568 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 569 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 570 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 571 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 572 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 573 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 574 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 575 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 576 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 577 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 578 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 579 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 580 # define OMAP_DMA_MMC2_TX 54 581 # define OMAP_DMA_MMC2_RX 55 582 # define OMAP_DMA_CRYPTO_DES_OUT 56 583 584 /* 585 * DMA request numbers for the OMAP2 586 */ 587 # define OMAP24XX_DMA_NO_DEVICE 0 588 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 589 # define OMAP24XX_DMA_EXT_DMAREQ0 2 590 # define OMAP24XX_DMA_EXT_DMAREQ1 3 591 # define OMAP24XX_DMA_GPMC 4 592 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 593 # define OMAP24XX_DMA_DSS 6 594 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 595 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 596 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 597 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 598 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 599 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 600 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 601 # define OMAP24XX_DMA_EXT_DMAREQ2 14 602 # define OMAP24XX_DMA_EXT_DMAREQ3 15 603 # define OMAP24XX_DMA_EXT_DMAREQ4 16 604 # define OMAP24XX_DMA_EAC_AC_RD 17 605 # define OMAP24XX_DMA_EAC_AC_WR 18 606 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 607 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 608 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 609 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 610 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 611 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 612 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 613 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 614 # define OMAP24XX_DMA_I2C1_TX 27 615 # define OMAP24XX_DMA_I2C1_RX 28 616 # define OMAP24XX_DMA_I2C2_TX 29 617 # define OMAP24XX_DMA_I2C2_RX 30 618 # define OMAP24XX_DMA_MCBSP1_TX 31 619 # define OMAP24XX_DMA_MCBSP1_RX 32 620 # define OMAP24XX_DMA_MCBSP2_TX 33 621 # define OMAP24XX_DMA_MCBSP2_RX 34 622 # define OMAP24XX_DMA_SPI1_TX0 35 623 # define OMAP24XX_DMA_SPI1_RX0 36 624 # define OMAP24XX_DMA_SPI1_TX1 37 625 # define OMAP24XX_DMA_SPI1_RX1 38 626 # define OMAP24XX_DMA_SPI1_TX2 39 627 # define OMAP24XX_DMA_SPI1_RX2 40 628 # define OMAP24XX_DMA_SPI1_TX3 41 629 # define OMAP24XX_DMA_SPI1_RX3 42 630 # define OMAP24XX_DMA_SPI2_TX0 43 631 # define OMAP24XX_DMA_SPI2_RX0 44 632 # define OMAP24XX_DMA_SPI2_TX1 45 633 # define OMAP24XX_DMA_SPI2_RX1 46 634 635 # define OMAP24XX_DMA_UART1_TX 49 636 # define OMAP24XX_DMA_UART1_RX 50 637 # define OMAP24XX_DMA_UART2_TX 51 638 # define OMAP24XX_DMA_UART2_RX 52 639 # define OMAP24XX_DMA_UART3_TX 53 640 # define OMAP24XX_DMA_UART3_RX 54 641 # define OMAP24XX_DMA_USB_W2FC_TX0 55 642 # define OMAP24XX_DMA_USB_W2FC_RX0 56 643 # define OMAP24XX_DMA_USB_W2FC_TX1 57 644 # define OMAP24XX_DMA_USB_W2FC_RX1 58 645 # define OMAP24XX_DMA_USB_W2FC_TX2 59 646 # define OMAP24XX_DMA_USB_W2FC_RX2 60 647 # define OMAP24XX_DMA_MMC1_TX 61 648 # define OMAP24XX_DMA_MMC1_RX 62 649 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_EXT_DMAREQ5 64 651 652 /* omap[123].c */ 653 /* OMAP2 gp timer */ 654 struct omap_gp_timer_s; 655 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 656 qemu_irq irq, omap_clk fclk, omap_clk iclk); 657 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 658 659 /* OMAP2 sysctimer */ 660 struct omap_synctimer_s; 661 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 662 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 663 void omap_synctimer_reset(struct omap_synctimer_s *s); 664 665 struct omap_uart_s; 666 struct omap_uart_s *omap_uart_init(hwaddr base, 667 qemu_irq irq, omap_clk fclk, omap_clk iclk, 668 qemu_irq txdma, qemu_irq rxdma, 669 const char *label, Chardev *chr); 670 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 671 struct omap_target_agent_s *ta, 672 qemu_irq irq, omap_clk fclk, omap_clk iclk, 673 qemu_irq txdma, qemu_irq rxdma, 674 const char *label, Chardev *chr); 675 void omap_uart_reset(struct omap_uart_s *s); 676 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 677 678 struct omap_mpuio_s; 679 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 680 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 681 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 682 683 struct omap_uwire_s; 684 void omap_uwire_attach(struct omap_uwire_s *s, 685 uWireSlave *slave, int chipselect); 686 687 /* OMAP2 spi */ 688 struct omap_mcspi_s; 689 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 690 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 691 void omap_mcspi_attach(struct omap_mcspi_s *s, 692 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 693 int chipselect); 694 void omap_mcspi_reset(struct omap_mcspi_s *s); 695 696 struct I2SCodec { 697 void *opaque; 698 699 /* The CPU can call this if it is generating the clock signal on the 700 * i2s port. The CODEC can ignore it if it is set up as a clock 701 * master and generates its own clock. */ 702 void (*set_rate)(void *opaque, int in, int out); 703 704 void (*tx_swallow)(void *opaque); 705 qemu_irq rx_swallow; 706 qemu_irq tx_start; 707 708 int tx_rate; 709 int cts; 710 int rx_rate; 711 int rts; 712 713 struct i2s_fifo_s { 714 uint8_t *fifo; 715 int len; 716 int start; 717 int size; 718 } in, out; 719 }; 720 struct omap_mcbsp_s; 721 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 722 723 void omap_tap_init(struct omap_target_agent_s *ta, 724 struct omap_mpu_state_s *mpu); 725 726 /* omap_lcdc.c */ 727 struct omap_lcd_panel_s; 728 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 729 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 730 hwaddr base, 731 qemu_irq irq, 732 struct omap_dma_lcd_channel_s *dma, 733 omap_clk clk); 734 735 /* omap_dss.c */ 736 struct rfbi_chip_s { 737 void *opaque; 738 void (*write)(void *opaque, int dc, uint16_t value); 739 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 740 uint16_t (*read)(void *opaque, int dc); 741 }; 742 struct omap_dss_s; 743 void omap_dss_reset(struct omap_dss_s *s); 744 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 745 MemoryRegion *sysmem, 746 hwaddr l3_base, 747 qemu_irq irq, qemu_irq drq, 748 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 749 omap_clk ick1, omap_clk ick2); 750 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 751 752 /* omap_mmc.c */ 753 struct omap_mmc_s; 754 struct omap_mmc_s *omap_mmc_init(hwaddr base, 755 MemoryRegion *sysmem, 756 BlockBackend *blk, 757 qemu_irq irq, qemu_irq dma[], omap_clk clk); 758 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 759 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 760 omap_clk fclk, omap_clk iclk); 761 void omap_mmc_reset(struct omap_mmc_s *s); 762 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 763 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 764 765 /* omap_i2c.c */ 766 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 767 768 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 769 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 770 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 771 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 772 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 773 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 774 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 775 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 776 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 777 778 # define cpu_is_omap15xx(cpu) \ 779 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 780 # define cpu_is_omap16xx(cpu) \ 781 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 782 # define cpu_is_omap24xx(cpu) \ 783 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 784 785 # define cpu_class_omap1(cpu) \ 786 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 787 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 788 # define cpu_class_omap3(cpu) \ 789 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 790 791 struct omap_mpu_state_s { 792 enum omap_mpu_model { 793 omap310, 794 omap1510, 795 omap1610, 796 omap1710, 797 omap2410, 798 omap2420, 799 omap2422, 800 omap2423, 801 omap2430, 802 omap3430, 803 omap3630, 804 } mpu_model; 805 806 ARMCPU *cpu; 807 808 qemu_irq *drq; 809 810 qemu_irq wakeup; 811 812 MemoryRegion ulpd_pm_iomem; 813 MemoryRegion pin_cfg_iomem; 814 MemoryRegion id_iomem; 815 MemoryRegion id_iomem_e18; 816 MemoryRegion id_iomem_ed4; 817 MemoryRegion id_iomem_e20; 818 MemoryRegion mpui_iomem; 819 MemoryRegion tcmi_iomem; 820 MemoryRegion clkm_iomem; 821 MemoryRegion clkdsp_iomem; 822 MemoryRegion mpui_io_iomem; 823 MemoryRegion tap_iomem; 824 MemoryRegion imif_ram; 825 MemoryRegion emiff_ram; 826 MemoryRegion sdram; 827 MemoryRegion sram; 828 829 struct omap_dma_port_if_s { 830 uint32_t (*read[3])(struct omap_mpu_state_s *s, 831 hwaddr offset); 832 void (*write[3])(struct omap_mpu_state_s *s, 833 hwaddr offset, uint32_t value); 834 int (*addr_valid)(struct omap_mpu_state_s *s, 835 hwaddr addr); 836 } port[__omap_dma_port_last]; 837 838 unsigned long sdram_size; 839 unsigned long sram_size; 840 841 /* MPUI-TIPB peripherals */ 842 struct omap_uart_s *uart[3]; 843 844 DeviceState *gpio; 845 846 struct omap_mcbsp_s *mcbsp1; 847 struct omap_mcbsp_s *mcbsp3; 848 849 /* MPU public TIPB peripherals */ 850 struct omap_32khz_timer_s *os_timer; 851 852 struct omap_mmc_s *mmc; 853 854 struct omap_mpuio_s *mpuio; 855 856 struct omap_uwire_s *microwire; 857 858 struct omap_pwl_s *pwl; 859 struct omap_pwt_s *pwt; 860 DeviceState *i2c[2]; 861 862 struct omap_rtc_s *rtc; 863 864 struct omap_mcbsp_s *mcbsp2; 865 866 struct omap_lpg_s *led[2]; 867 868 /* MPU private TIPB peripherals */ 869 DeviceState *ih[2]; 870 871 struct soc_dma_s *dma; 872 873 struct omap_mpu_timer_s *timer[3]; 874 struct omap_watchdog_timer_s *wdt; 875 876 struct omap_lcd_panel_s *lcd; 877 878 uint32_t ulpd_pm_regs[21]; 879 int64_t ulpd_gauge_start; 880 881 uint32_t func_mux_ctrl[14]; 882 uint32_t comp_mode_ctrl[1]; 883 uint32_t pull_dwn_ctrl[4]; 884 uint32_t gate_inh_ctrl[1]; 885 uint32_t voltage_ctrl[1]; 886 uint32_t test_dbg_ctrl[1]; 887 uint32_t mod_conf_ctrl[1]; 888 int compat1509; 889 890 uint32_t mpui_ctrl; 891 892 struct omap_tipb_bridge_s *private_tipb; 893 struct omap_tipb_bridge_s *public_tipb; 894 895 uint32_t tcmi_regs[17]; 896 897 struct dpll_ctl_s *dpll[3]; 898 899 omap_clk clks; 900 struct { 901 int cold_start; 902 int clocking_scheme; 903 uint16_t arm_ckctl; 904 uint16_t arm_idlect1; 905 uint16_t arm_idlect2; 906 uint16_t arm_ewupct; 907 uint16_t arm_rstct1; 908 uint16_t arm_rstct2; 909 uint16_t arm_ckout1; 910 int dpll1_mode; 911 uint16_t dsp_idlect1; 912 uint16_t dsp_idlect2; 913 uint16_t dsp_rstct2; 914 } clkm; 915 916 /* OMAP2-only peripherals */ 917 struct omap_l4_s *l4; 918 919 struct omap_gp_timer_s *gptimer[12]; 920 struct omap_synctimer_s *synctimer; 921 922 struct omap_prcm_s *prcm; 923 struct omap_sdrc_s *sdrc; 924 struct omap_gpmc_s *gpmc; 925 struct omap_sysctl_s *sysc; 926 927 struct omap_mcspi_s *mcspi[2]; 928 929 struct omap_dss_s *dss; 930 931 struct omap_eac_s *eac; 932 }; 933 934 /* omap1.c */ 935 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 936 unsigned long sdram_size, 937 const char *core); 938 939 /* omap2.c */ 940 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 941 unsigned long sdram_size, 942 const char *core); 943 944 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 945 void omap_badwidth_write8(void *opaque, hwaddr addr, 946 uint32_t value); 947 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 948 void omap_badwidth_write16(void *opaque, hwaddr addr, 949 uint32_t value); 950 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 951 void omap_badwidth_write32(void *opaque, hwaddr addr, 952 uint32_t value); 953 954 void omap_mpu_wakeup(void *opaque, int irq, int req); 955 956 # define OMAP_BAD_REG(paddr) \ 957 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 958 __func__, paddr) 959 # define OMAP_RO_REG(paddr) \ 960 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 961 HWADDR_PRIx "\n", \ 962 __func__, paddr) 963 964 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 965 (Board-specifc tags are not here) */ 966 #define OMAP_TAG_CLOCK 0x4f01 967 #define OMAP_TAG_MMC 0x4f02 968 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 969 #define OMAP_TAG_USB 0x4f04 970 #define OMAP_TAG_LCD 0x4f05 971 #define OMAP_TAG_GPIO_SWITCH 0x4f06 972 #define OMAP_TAG_UART 0x4f07 973 #define OMAP_TAG_FBMEM 0x4f08 974 #define OMAP_TAG_STI_CONSOLE 0x4f09 975 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 976 #define OMAP_TAG_PARTITION 0x4f0b 977 #define OMAP_TAG_TEA5761 0x4f10 978 #define OMAP_TAG_TMP105 0x4f11 979 #define OMAP_TAG_BOOT_REASON 0x4f80 980 #define OMAP_TAG_FLASH_PART_STR 0x4f81 981 #define OMAP_TAG_VERSION_STR 0x4f82 982 983 enum { 984 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 985 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 986 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 987 }; 988 989 #define OMAP_GPIOSW_INVERTED 0x0001 990 #define OMAP_GPIOSW_OUTPUT 0x0002 991 992 # define OMAP_MPUI_REG_MASK 0x000007ff 993 994 #endif /* hw_omap_h */ 995