1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "target/arm/cpu-qom.h" 25 #include "qemu/log.h" 26 #include "qom/object.h" 27 28 # define OMAP_EMIFS_BASE 0x00000000 29 # define OMAP2_Q0_BASE 0x00000000 30 # define OMAP_CS0_BASE 0x00000000 31 # define OMAP_CS1_BASE 0x04000000 32 # define OMAP_CS2_BASE 0x08000000 33 # define OMAP_CS3_BASE 0x0c000000 34 # define OMAP_EMIFF_BASE 0x10000000 35 # define OMAP_IMIF_BASE 0x20000000 36 # define OMAP_LOCALBUS_BASE 0x30000000 37 # define OMAP2_Q1_BASE 0x40000000 38 # define OMAP2_L4_BASE 0x48000000 39 # define OMAP2_SRAM_BASE 0x40200000 40 # define OMAP2_L3_BASE 0x68000000 41 # define OMAP2_Q2_BASE 0x80000000 42 # define OMAP2_Q3_BASE 0xc0000000 43 # define OMAP_MPUI_BASE 0xe1000000 44 45 # define OMAP730_SRAM_SIZE 0x00032000 46 # define OMAP15XX_SRAM_SIZE 0x00030000 47 # define OMAP16XX_SRAM_SIZE 0x00004000 48 # define OMAP1611_SRAM_SIZE 0x0003e800 49 # define OMAP242X_SRAM_SIZE 0x000a0000 50 # define OMAP243X_SRAM_SIZE 0x00010000 51 # define OMAP_CS0_SIZE 0x04000000 52 # define OMAP_CS1_SIZE 0x04000000 53 # define OMAP_CS2_SIZE 0x04000000 54 # define OMAP_CS3_SIZE 0x04000000 55 56 /* omap_clk.c */ 57 struct omap_mpu_state_s; 58 typedef struct clk *omap_clk; 59 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 60 void omap_clk_init(struct omap_mpu_state_s *mpu); 61 void omap_clk_adduser(struct clk *clk, qemu_irq user); 62 void omap_clk_get(omap_clk clk); 63 void omap_clk_put(omap_clk clk); 64 void omap_clk_onoff(omap_clk clk, int on); 65 void omap_clk_canidle(omap_clk clk, int can); 66 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 67 int64_t omap_clk_getrate(omap_clk clk); 68 void omap_clk_reparent(omap_clk clk, omap_clk parent); 69 70 /* omap_intc.c */ 71 #define TYPE_OMAP_INTC "common-omap-intc" 72 typedef struct OMAPIntcState OMAPIntcState; 73 DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) 74 75 76 /* 77 * TODO: Ideally we should have a clock framework that 78 * let us wire these clocks up with QOM properties or links. 79 * 80 * qdev should support a generic means of defining a 'port' with 81 * an arbitrary interface for connecting two devices. Then we 82 * could reframe the omap clock API in terms of clock ports, 83 * and get some type safety. For now the best qdev provides is 84 * passing an arbitrary pointer. 85 * (It's not possible to pass in the string which is the clock 86 * name, because this device does not have the necessary information 87 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 88 * translation.) 89 */ 90 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); 91 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); 92 93 /* omap_i2c.c */ 94 #define TYPE_OMAP_I2C "omap_i2c" 95 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 96 97 98 /* TODO: clock framework (see above) */ 99 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 100 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 101 102 /* omap_gpio.c */ 103 #define TYPE_OMAP1_GPIO "omap-gpio" 104 typedef struct Omap1GpioState Omap1GpioState; 105 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 106 TYPE_OMAP1_GPIO) 107 108 /* TODO: clock framework (see above) */ 109 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 110 111 /* OMAP2 l4 Interconnect */ 112 struct omap_l4_s; 113 struct omap_l4_region_s { 114 hwaddr offset; 115 size_t size; 116 int access; 117 }; 118 struct omap_l4_agent_info_s { 119 int ta; 120 int region; 121 int regions; 122 int ta_region; 123 }; 124 struct omap_target_agent_s { 125 MemoryRegion iomem; 126 struct omap_l4_s *bus; 127 int regions; 128 const struct omap_l4_region_s *start; 129 hwaddr base; 130 uint32_t component; 131 uint32_t control; 132 uint32_t status; 133 }; 134 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 135 hwaddr base, int ta_num); 136 137 struct omap_target_agent_s; 138 struct omap_target_agent_s *omap_l4ta_get( 139 struct omap_l4_s *bus, 140 const struct omap_l4_region_s *regions, 141 const struct omap_l4_agent_info_s *agents, 142 int cs); 143 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 144 int region, MemoryRegion *mr); 145 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 146 int region); 147 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 148 int region); 149 150 /* OMAP2 SDRAM controller */ 151 struct omap_sdrc_s; 152 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 153 hwaddr base); 154 void omap_sdrc_reset(struct omap_sdrc_s *s); 155 156 /* OMAP2 general purpose memory controller */ 157 struct omap_gpmc_s; 158 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 159 hwaddr base, 160 qemu_irq irq, qemu_irq drq); 161 void omap_gpmc_reset(struct omap_gpmc_s *s); 162 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 163 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 164 165 /* 166 * Common IRQ numbers for level 1 interrupt handler 167 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 168 */ 169 # define OMAP_INT_CAMERA 1 170 # define OMAP_INT_FIQ 3 171 # define OMAP_INT_RTDX 6 172 # define OMAP_INT_DSP_MMU_ABORT 7 173 # define OMAP_INT_HOST 8 174 # define OMAP_INT_ABORT 9 175 # define OMAP_INT_BRIDGE_PRIV 13 176 # define OMAP_INT_GPIO_BANK1 14 177 # define OMAP_INT_UART3 15 178 # define OMAP_INT_TIMER3 16 179 # define OMAP_INT_DMA_CH0_6 19 180 # define OMAP_INT_DMA_CH1_7 20 181 # define OMAP_INT_DMA_CH2_8 21 182 # define OMAP_INT_DMA_CH3 22 183 # define OMAP_INT_DMA_CH4 23 184 # define OMAP_INT_DMA_CH5 24 185 # define OMAP_INT_DMA_LCD 25 186 # define OMAP_INT_TIMER1 26 187 # define OMAP_INT_WD_TIMER 27 188 # define OMAP_INT_BRIDGE_PUB 28 189 # define OMAP_INT_TIMER2 30 190 # define OMAP_INT_LCD_CTRL 31 191 192 /* 193 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 194 */ 195 # define OMAP_INT_15XX_IH2_IRQ 0 196 # define OMAP_INT_15XX_LB_MMU 17 197 # define OMAP_INT_15XX_LOCAL_BUS 29 198 199 /* 200 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 201 */ 202 # define OMAP_INT_1510_SPI_TX 4 203 # define OMAP_INT_1510_SPI_RX 5 204 # define OMAP_INT_1510_DSP_MAILBOX1 10 205 # define OMAP_INT_1510_DSP_MAILBOX2 11 206 207 /* 208 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 209 */ 210 # define OMAP_INT_310_McBSP2_TX 4 211 # define OMAP_INT_310_McBSP2_RX 5 212 # define OMAP_INT_310_HSB_MAILBOX1 12 213 # define OMAP_INT_310_HSAB_MMU 18 214 215 /* 216 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 217 */ 218 # define OMAP_INT_1610_IH2_IRQ 0 219 # define OMAP_INT_1610_IH2_FIQ 2 220 # define OMAP_INT_1610_McBSP2_TX 4 221 # define OMAP_INT_1610_McBSP2_RX 5 222 # define OMAP_INT_1610_DSP_MAILBOX1 10 223 # define OMAP_INT_1610_DSP_MAILBOX2 11 224 # define OMAP_INT_1610_LCD_LINE 12 225 # define OMAP_INT_1610_GPTIMER1 17 226 # define OMAP_INT_1610_GPTIMER2 18 227 # define OMAP_INT_1610_SSR_FIFO_0 29 228 229 /* 230 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 231 */ 232 # define OMAP_INT_730_IH2_FIQ 0 233 # define OMAP_INT_730_IH2_IRQ 1 234 # define OMAP_INT_730_USB_NON_ISO 2 235 # define OMAP_INT_730_USB_ISO 3 236 # define OMAP_INT_730_ICR 4 237 # define OMAP_INT_730_EAC 5 238 # define OMAP_INT_730_GPIO_BANK1 6 239 # define OMAP_INT_730_GPIO_BANK2 7 240 # define OMAP_INT_730_GPIO_BANK3 8 241 # define OMAP_INT_730_McBSP2TX 10 242 # define OMAP_INT_730_McBSP2RX 11 243 # define OMAP_INT_730_McBSP2RX_OVF 12 244 # define OMAP_INT_730_LCD_LINE 14 245 # define OMAP_INT_730_GSM_PROTECT 15 246 # define OMAP_INT_730_TIMER3 16 247 # define OMAP_INT_730_GPIO_BANK5 17 248 # define OMAP_INT_730_GPIO_BANK6 18 249 # define OMAP_INT_730_SPGIO_WR 29 250 251 /* 252 * Common IRQ numbers for level 2 interrupt handler 253 */ 254 # define OMAP_INT_KEYBOARD 1 255 # define OMAP_INT_uWireTX 2 256 # define OMAP_INT_uWireRX 3 257 # define OMAP_INT_I2C 4 258 # define OMAP_INT_MPUIO 5 259 # define OMAP_INT_USB_HHC_1 6 260 # define OMAP_INT_McBSP3TX 10 261 # define OMAP_INT_McBSP3RX 11 262 # define OMAP_INT_McBSP1TX 12 263 # define OMAP_INT_McBSP1RX 13 264 # define OMAP_INT_UART1 14 265 # define OMAP_INT_UART2 15 266 # define OMAP_INT_USB_W2FC 20 267 # define OMAP_INT_1WIRE 21 268 # define OMAP_INT_OS_TIMER 22 269 # define OMAP_INT_OQN 23 270 # define OMAP_INT_GAUGE_32K 24 271 # define OMAP_INT_RTC_TIMER 25 272 # define OMAP_INT_RTC_ALARM 26 273 # define OMAP_INT_DSP_MMU 28 274 275 /* 276 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 277 */ 278 # define OMAP_INT_1510_BT_MCSI1TX 16 279 # define OMAP_INT_1510_BT_MCSI1RX 17 280 # define OMAP_INT_1510_SoSSI_MATCH 19 281 # define OMAP_INT_1510_MEM_STICK 27 282 # define OMAP_INT_1510_COM_SPI_RO 31 283 284 /* 285 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 286 */ 287 # define OMAP_INT_310_FAC 0 288 # define OMAP_INT_310_USB_HHC_2 7 289 # define OMAP_INT_310_MCSI1_FE 16 290 # define OMAP_INT_310_MCSI2_FE 17 291 # define OMAP_INT_310_USB_W2FC_ISO 29 292 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 293 # define OMAP_INT_310_McBSP2RX_OF 31 294 295 /* 296 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 297 */ 298 # define OMAP_INT_1610_FAC 0 299 # define OMAP_INT_1610_USB_HHC_2 7 300 # define OMAP_INT_1610_USB_OTG 8 301 # define OMAP_INT_1610_SoSSI 9 302 # define OMAP_INT_1610_BT_MCSI1TX 16 303 # define OMAP_INT_1610_BT_MCSI1RX 17 304 # define OMAP_INT_1610_SoSSI_MATCH 19 305 # define OMAP_INT_1610_MEM_STICK 27 306 # define OMAP_INT_1610_McBSP2RX_OF 31 307 # define OMAP_INT_1610_STI 32 308 # define OMAP_INT_1610_STI_WAKEUP 33 309 # define OMAP_INT_1610_GPTIMER3 34 310 # define OMAP_INT_1610_GPTIMER4 35 311 # define OMAP_INT_1610_GPTIMER5 36 312 # define OMAP_INT_1610_GPTIMER6 37 313 # define OMAP_INT_1610_GPTIMER7 38 314 # define OMAP_INT_1610_GPTIMER8 39 315 # define OMAP_INT_1610_GPIO_BANK2 40 316 # define OMAP_INT_1610_GPIO_BANK3 41 317 # define OMAP_INT_1610_MMC2 42 318 # define OMAP_INT_1610_CF 43 319 # define OMAP_INT_1610_WAKE_UP_REQ 46 320 # define OMAP_INT_1610_GPIO_BANK4 48 321 # define OMAP_INT_1610_SPI 49 322 # define OMAP_INT_1610_DMA_CH6 53 323 # define OMAP_INT_1610_DMA_CH7 54 324 # define OMAP_INT_1610_DMA_CH8 55 325 # define OMAP_INT_1610_DMA_CH9 56 326 # define OMAP_INT_1610_DMA_CH10 57 327 # define OMAP_INT_1610_DMA_CH11 58 328 # define OMAP_INT_1610_DMA_CH12 59 329 # define OMAP_INT_1610_DMA_CH13 60 330 # define OMAP_INT_1610_DMA_CH14 61 331 # define OMAP_INT_1610_DMA_CH15 62 332 # define OMAP_INT_1610_NAND 63 333 334 /* 335 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 336 */ 337 # define OMAP_INT_730_HW_ERRORS 0 338 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 339 # define OMAP_INT_730_CFCD 2 340 # define OMAP_INT_730_CFIREQ 3 341 # define OMAP_INT_730_I2C 4 342 # define OMAP_INT_730_PCC 5 343 # define OMAP_INT_730_MPU_EXT_NIRQ 6 344 # define OMAP_INT_730_SPI_100K_1 7 345 # define OMAP_INT_730_SYREN_SPI 8 346 # define OMAP_INT_730_VLYNQ 9 347 # define OMAP_INT_730_GPIO_BANK4 10 348 # define OMAP_INT_730_McBSP1TX 11 349 # define OMAP_INT_730_McBSP1RX 12 350 # define OMAP_INT_730_McBSP1RX_OF 13 351 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 352 # define OMAP_INT_730_UART_MODEM_1 15 353 # define OMAP_INT_730_MCSI 16 354 # define OMAP_INT_730_uWireTX 17 355 # define OMAP_INT_730_uWireRX 18 356 # define OMAP_INT_730_SMC_CD 19 357 # define OMAP_INT_730_SMC_IREQ 20 358 # define OMAP_INT_730_HDQ_1WIRE 21 359 # define OMAP_INT_730_TIMER32K 22 360 # define OMAP_INT_730_MMC_SDIO 23 361 # define OMAP_INT_730_UPLD 24 362 # define OMAP_INT_730_USB_HHC_1 27 363 # define OMAP_INT_730_USB_HHC_2 28 364 # define OMAP_INT_730_USB_GENI 29 365 # define OMAP_INT_730_USB_OTG 30 366 # define OMAP_INT_730_CAMERA_IF 31 367 # define OMAP_INT_730_RNG 32 368 # define OMAP_INT_730_DUAL_MODE_TIMER 33 369 # define OMAP_INT_730_DBB_RF_EN 34 370 # define OMAP_INT_730_MPUIO_KEYPAD 35 371 # define OMAP_INT_730_SHA1_MD5 36 372 # define OMAP_INT_730_SPI_100K_2 37 373 # define OMAP_INT_730_RNG_IDLE 38 374 # define OMAP_INT_730_MPUIO 39 375 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 376 # define OMAP_INT_730_LLPC_OE_FALLING 41 377 # define OMAP_INT_730_LLPC_OE_RISING 42 378 # define OMAP_INT_730_LLPC_VSYNC 43 379 # define OMAP_INT_730_WAKE_UP_REQ 46 380 # define OMAP_INT_730_DMA_CH6 53 381 # define OMAP_INT_730_DMA_CH7 54 382 # define OMAP_INT_730_DMA_CH8 55 383 # define OMAP_INT_730_DMA_CH9 56 384 # define OMAP_INT_730_DMA_CH10 57 385 # define OMAP_INT_730_DMA_CH11 58 386 # define OMAP_INT_730_DMA_CH12 59 387 # define OMAP_INT_730_DMA_CH13 60 388 # define OMAP_INT_730_DMA_CH14 61 389 # define OMAP_INT_730_DMA_CH15 62 390 # define OMAP_INT_730_NAND 63 391 392 /* 393 * OMAP-24xx common IRQ numbers 394 */ 395 # define OMAP_INT_24XX_STI 4 396 # define OMAP_INT_24XX_SYS_NIRQ 7 397 # define OMAP_INT_24XX_L3_IRQ 10 398 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 399 # define OMAP_INT_24XX_SDMA_IRQ0 12 400 # define OMAP_INT_24XX_SDMA_IRQ1 13 401 # define OMAP_INT_24XX_SDMA_IRQ2 14 402 # define OMAP_INT_24XX_SDMA_IRQ3 15 403 # define OMAP_INT_243X_MCBSP2_IRQ 16 404 # define OMAP_INT_243X_MCBSP3_IRQ 17 405 # define OMAP_INT_243X_MCBSP4_IRQ 18 406 # define OMAP_INT_243X_MCBSP5_IRQ 19 407 # define OMAP_INT_24XX_GPMC_IRQ 20 408 # define OMAP_INT_24XX_GUFFAW_IRQ 21 409 # define OMAP_INT_24XX_IVA_IRQ 22 410 # define OMAP_INT_24XX_EAC_IRQ 23 411 # define OMAP_INT_24XX_CAM_IRQ 24 412 # define OMAP_INT_24XX_DSS_IRQ 25 413 # define OMAP_INT_24XX_MAIL_U0_MPU 26 414 # define OMAP_INT_24XX_DSP_UMA 27 415 # define OMAP_INT_24XX_DSP_MMU 28 416 # define OMAP_INT_24XX_GPIO_BANK1 29 417 # define OMAP_INT_24XX_GPIO_BANK2 30 418 # define OMAP_INT_24XX_GPIO_BANK3 31 419 # define OMAP_INT_24XX_GPIO_BANK4 32 420 # define OMAP_INT_243X_GPIO_BANK5 33 421 # define OMAP_INT_24XX_MAIL_U3_MPU 34 422 # define OMAP_INT_24XX_WDT3 35 423 # define OMAP_INT_24XX_WDT4 36 424 # define OMAP_INT_24XX_GPTIMER1 37 425 # define OMAP_INT_24XX_GPTIMER2 38 426 # define OMAP_INT_24XX_GPTIMER3 39 427 # define OMAP_INT_24XX_GPTIMER4 40 428 # define OMAP_INT_24XX_GPTIMER5 41 429 # define OMAP_INT_24XX_GPTIMER6 42 430 # define OMAP_INT_24XX_GPTIMER7 43 431 # define OMAP_INT_24XX_GPTIMER8 44 432 # define OMAP_INT_24XX_GPTIMER9 45 433 # define OMAP_INT_24XX_GPTIMER10 46 434 # define OMAP_INT_24XX_GPTIMER11 47 435 # define OMAP_INT_24XX_GPTIMER12 48 436 # define OMAP_INT_24XX_PKA_IRQ 50 437 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 438 # define OMAP_INT_24XX_RNG_IRQ 52 439 # define OMAP_INT_24XX_MG_IRQ 53 440 # define OMAP_INT_24XX_I2C1_IRQ 56 441 # define OMAP_INT_24XX_I2C2_IRQ 57 442 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 443 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 444 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 445 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 446 # define OMAP_INT_243X_MCBSP1_IRQ 64 447 # define OMAP_INT_24XX_MCSPI1_IRQ 65 448 # define OMAP_INT_24XX_MCSPI2_IRQ 66 449 # define OMAP_INT_24XX_SSI1_IRQ0 67 450 # define OMAP_INT_24XX_SSI1_IRQ1 68 451 # define OMAP_INT_24XX_SSI2_IRQ0 69 452 # define OMAP_INT_24XX_SSI2_IRQ1 70 453 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 454 # define OMAP_INT_24XX_UART1_IRQ 72 455 # define OMAP_INT_24XX_UART2_IRQ 73 456 # define OMAP_INT_24XX_UART3_IRQ 74 457 # define OMAP_INT_24XX_USB_IRQ_GEN 75 458 # define OMAP_INT_24XX_USB_IRQ_NISO 76 459 # define OMAP_INT_24XX_USB_IRQ_ISO 77 460 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 461 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 462 # define OMAP_INT_24XX_USB_IRQ_OTG 80 463 # define OMAP_INT_24XX_VLYNQ_IRQ 81 464 # define OMAP_INT_24XX_MMC_IRQ 83 465 # define OMAP_INT_24XX_MS_IRQ 84 466 # define OMAP_INT_24XX_FAC_IRQ 85 467 # define OMAP_INT_24XX_MCSPI3_IRQ 91 468 # define OMAP_INT_243X_HS_USB_MC 92 469 # define OMAP_INT_243X_HS_USB_DMA 93 470 # define OMAP_INT_243X_CARKIT 94 471 # define OMAP_INT_34XX_GPTIMER12 95 472 473 /* omap_dma.c */ 474 enum omap_dma_model { 475 omap_dma_3_0, 476 omap_dma_3_1, 477 omap_dma_3_2, 478 omap_dma_4, 479 }; 480 481 struct soc_dma_s; 482 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 483 MemoryRegion *sysmem, 484 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 485 enum omap_dma_model model); 486 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 487 MemoryRegion *sysmem, 488 struct omap_mpu_state_s *mpu, int fifo, 489 int chans, omap_clk iclk, omap_clk fclk); 490 void omap_dma_reset(struct soc_dma_s *s); 491 492 struct dma_irq_map { 493 int ih; 494 int intr; 495 }; 496 497 /* Only used in OMAP DMA 3.x gigacells */ 498 enum omap_dma_port { 499 emiff = 0, 500 emifs, 501 imif, /* omap16xx: ocp_t1 */ 502 tipb, 503 local, /* omap16xx: ocp_t2 */ 504 tipb_mpui, 505 __omap_dma_port_last, 506 }; 507 508 typedef enum { 509 constant = 0, 510 post_incremented, 511 single_index, 512 double_index, 513 } omap_dma_addressing_t; 514 515 /* Only used in OMAP DMA 3.x gigacells */ 516 struct omap_dma_lcd_channel_s { 517 enum omap_dma_port src; 518 hwaddr src_f1_top; 519 hwaddr src_f1_bottom; 520 hwaddr src_f2_top; 521 hwaddr src_f2_bottom; 522 523 /* Used in OMAP DMA 3.2 gigacell */ 524 unsigned char brust_f1; 525 unsigned char pack_f1; 526 unsigned char data_type_f1; 527 unsigned char brust_f2; 528 unsigned char pack_f2; 529 unsigned char data_type_f2; 530 unsigned char end_prog; 531 unsigned char repeat; 532 unsigned char auto_init; 533 unsigned char priority; 534 unsigned char fs; 535 unsigned char running; 536 unsigned char bs; 537 unsigned char omap_3_1_compatible_disable; 538 unsigned char dst; 539 unsigned char lch_type; 540 int16_t element_index_f1; 541 int16_t element_index_f2; 542 int32_t frame_index_f1; 543 int32_t frame_index_f2; 544 uint16_t elements_f1; 545 uint16_t frames_f1; 546 uint16_t elements_f2; 547 uint16_t frames_f2; 548 omap_dma_addressing_t mode_f1; 549 omap_dma_addressing_t mode_f2; 550 551 /* Destination port is fixed. */ 552 int interrupts; 553 int condition; 554 int dual; 555 556 int current_frame; 557 hwaddr phys_framebuffer[2]; 558 qemu_irq irq; 559 struct omap_mpu_state_s *mpu; 560 } *omap_dma_get_lcdch(struct soc_dma_s *s); 561 562 /* 563 * DMA request numbers for OMAP1 564 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 565 */ 566 # define OMAP_DMA_NO_DEVICE 0 567 # define OMAP_DMA_MCSI1_TX 1 568 # define OMAP_DMA_MCSI1_RX 2 569 # define OMAP_DMA_I2C_RX 3 570 # define OMAP_DMA_I2C_TX 4 571 # define OMAP_DMA_EXT_NDMA_REQ0 5 572 # define OMAP_DMA_EXT_NDMA_REQ1 6 573 # define OMAP_DMA_UWIRE_TX 7 574 # define OMAP_DMA_MCBSP1_TX 8 575 # define OMAP_DMA_MCBSP1_RX 9 576 # define OMAP_DMA_MCBSP3_TX 10 577 # define OMAP_DMA_MCBSP3_RX 11 578 # define OMAP_DMA_UART1_TX 12 579 # define OMAP_DMA_UART1_RX 13 580 # define OMAP_DMA_UART2_TX 14 581 # define OMAP_DMA_UART2_RX 15 582 # define OMAP_DMA_MCBSP2_TX 16 583 # define OMAP_DMA_MCBSP2_RX 17 584 # define OMAP_DMA_UART3_TX 18 585 # define OMAP_DMA_UART3_RX 19 586 # define OMAP_DMA_CAMERA_IF_RX 20 587 # define OMAP_DMA_MMC_TX 21 588 # define OMAP_DMA_MMC_RX 22 589 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 590 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 591 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 592 # define OMAP_DMA_USB_W2FC_RX0 26 593 # define OMAP_DMA_USB_W2FC_RX1 27 594 # define OMAP_DMA_USB_W2FC_RX2 28 595 # define OMAP_DMA_USB_W2FC_TX0 29 596 # define OMAP_DMA_USB_W2FC_TX1 30 597 # define OMAP_DMA_USB_W2FC_TX2 31 598 599 /* These are only for 1610 */ 600 # define OMAP_DMA_CRYPTO_DES_IN 32 601 # define OMAP_DMA_SPI_TX 33 602 # define OMAP_DMA_SPI_RX 34 603 # define OMAP_DMA_CRYPTO_HASH 35 604 # define OMAP_DMA_CCP_ATTN 36 605 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 606 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 607 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 608 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 609 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 610 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 611 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 612 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 613 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 614 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 615 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 616 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 617 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 618 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 619 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 620 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 621 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 622 # define OMAP_DMA_MMC2_TX 54 623 # define OMAP_DMA_MMC2_RX 55 624 # define OMAP_DMA_CRYPTO_DES_OUT 56 625 626 /* 627 * DMA request numbers for the OMAP2 628 */ 629 # define OMAP24XX_DMA_NO_DEVICE 0 630 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 631 # define OMAP24XX_DMA_EXT_DMAREQ0 2 632 # define OMAP24XX_DMA_EXT_DMAREQ1 3 633 # define OMAP24XX_DMA_GPMC 4 634 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 635 # define OMAP24XX_DMA_DSS 6 636 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 637 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 638 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 639 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 640 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 641 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 642 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 643 # define OMAP24XX_DMA_EXT_DMAREQ2 14 644 # define OMAP24XX_DMA_EXT_DMAREQ3 15 645 # define OMAP24XX_DMA_EXT_DMAREQ4 16 646 # define OMAP24XX_DMA_EAC_AC_RD 17 647 # define OMAP24XX_DMA_EAC_AC_WR 18 648 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 649 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 650 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 651 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 652 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 653 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 654 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 655 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 656 # define OMAP24XX_DMA_I2C1_TX 27 657 # define OMAP24XX_DMA_I2C1_RX 28 658 # define OMAP24XX_DMA_I2C2_TX 29 659 # define OMAP24XX_DMA_I2C2_RX 30 660 # define OMAP24XX_DMA_MCBSP1_TX 31 661 # define OMAP24XX_DMA_MCBSP1_RX 32 662 # define OMAP24XX_DMA_MCBSP2_TX 33 663 # define OMAP24XX_DMA_MCBSP2_RX 34 664 # define OMAP24XX_DMA_SPI1_TX0 35 665 # define OMAP24XX_DMA_SPI1_RX0 36 666 # define OMAP24XX_DMA_SPI1_TX1 37 667 # define OMAP24XX_DMA_SPI1_RX1 38 668 # define OMAP24XX_DMA_SPI1_TX2 39 669 # define OMAP24XX_DMA_SPI1_RX2 40 670 # define OMAP24XX_DMA_SPI1_TX3 41 671 # define OMAP24XX_DMA_SPI1_RX3 42 672 # define OMAP24XX_DMA_SPI2_TX0 43 673 # define OMAP24XX_DMA_SPI2_RX0 44 674 # define OMAP24XX_DMA_SPI2_TX1 45 675 # define OMAP24XX_DMA_SPI2_RX1 46 676 677 # define OMAP24XX_DMA_UART1_TX 49 678 # define OMAP24XX_DMA_UART1_RX 50 679 # define OMAP24XX_DMA_UART2_TX 51 680 # define OMAP24XX_DMA_UART2_RX 52 681 # define OMAP24XX_DMA_UART3_TX 53 682 # define OMAP24XX_DMA_UART3_RX 54 683 # define OMAP24XX_DMA_USB_W2FC_TX0 55 684 # define OMAP24XX_DMA_USB_W2FC_RX0 56 685 # define OMAP24XX_DMA_USB_W2FC_TX1 57 686 # define OMAP24XX_DMA_USB_W2FC_RX1 58 687 # define OMAP24XX_DMA_USB_W2FC_TX2 59 688 # define OMAP24XX_DMA_USB_W2FC_RX2 60 689 # define OMAP24XX_DMA_MMC1_TX 61 690 # define OMAP24XX_DMA_MMC1_RX 62 691 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 692 # define OMAP24XX_DMA_EXT_DMAREQ5 64 693 694 /* omap[123].c */ 695 /* OMAP2 gp timer */ 696 struct omap_gp_timer_s; 697 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 698 qemu_irq irq, omap_clk fclk, omap_clk iclk); 699 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 700 701 /* OMAP2 sysctimer */ 702 struct omap_synctimer_s; 703 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 704 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 705 void omap_synctimer_reset(struct omap_synctimer_s *s); 706 707 struct omap_uart_s; 708 struct omap_uart_s *omap_uart_init(hwaddr base, 709 qemu_irq irq, omap_clk fclk, omap_clk iclk, 710 qemu_irq txdma, qemu_irq rxdma, 711 const char *label, Chardev *chr); 712 void omap_uart_reset(struct omap_uart_s *s); 713 714 struct omap_mpuio_s; 715 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 716 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 717 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 718 719 typedef struct uWireSlave { 720 uint16_t (*receive)(void *opaque); 721 void (*send)(void *opaque, uint16_t data); 722 void *opaque; 723 } uWireSlave; 724 725 struct omap_uwire_s; 726 void omap_uwire_attach(struct omap_uwire_s *s, 727 uWireSlave *slave, int chipselect); 728 729 /* OMAP2 spi */ 730 struct omap_mcspi_s; 731 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 732 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 733 void omap_mcspi_attach(struct omap_mcspi_s *s, 734 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 735 int chipselect); 736 void omap_mcspi_reset(struct omap_mcspi_s *s); 737 738 struct I2SCodec { 739 void *opaque; 740 741 /* The CPU can call this if it is generating the clock signal on the 742 * i2s port. The CODEC can ignore it if it is set up as a clock 743 * master and generates its own clock. */ 744 void (*set_rate)(void *opaque, int in, int out); 745 746 void (*tx_swallow)(void *opaque); 747 qemu_irq rx_swallow; 748 qemu_irq tx_start; 749 750 int tx_rate; 751 int cts; 752 int rx_rate; 753 int rts; 754 755 struct i2s_fifo_s { 756 uint8_t *fifo; 757 int len; 758 int start; 759 int size; 760 } in, out; 761 }; 762 struct omap_mcbsp_s; 763 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 764 765 void omap_tap_init(struct omap_target_agent_s *ta, 766 struct omap_mpu_state_s *mpu); 767 768 /* omap_lcdc.c */ 769 struct omap_lcd_panel_s; 770 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 771 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 772 hwaddr base, 773 qemu_irq irq, 774 struct omap_dma_lcd_channel_s *dma, 775 omap_clk clk); 776 777 /* omap_dss.c */ 778 struct rfbi_chip_s { 779 void *opaque; 780 void (*write)(void *opaque, int dc, uint16_t value); 781 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 782 uint16_t (*read)(void *opaque, int dc); 783 }; 784 struct omap_dss_s; 785 void omap_dss_reset(struct omap_dss_s *s); 786 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 787 MemoryRegion *sysmem, 788 hwaddr l3_base, 789 qemu_irq irq, qemu_irq drq, 790 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 791 omap_clk ick1, omap_clk ick2); 792 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 793 794 /* omap_mmc.c */ 795 struct omap_mmc_s; 796 struct omap_mmc_s *omap_mmc_init(hwaddr base, 797 MemoryRegion *sysmem, 798 BlockBackend *blk, 799 qemu_irq irq, qemu_irq dma[], omap_clk clk); 800 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 801 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 802 omap_clk fclk, omap_clk iclk); 803 void omap_mmc_reset(struct omap_mmc_s *s); 804 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 805 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 806 807 /* omap_i2c.c */ 808 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 809 810 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 811 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 812 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 813 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 814 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 815 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 816 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 817 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 818 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 819 820 # define cpu_is_omap15xx(cpu) \ 821 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 822 # define cpu_is_omap16xx(cpu) \ 823 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 824 # define cpu_is_omap24xx(cpu) \ 825 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 826 827 # define cpu_class_omap1(cpu) \ 828 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 829 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 830 # define cpu_class_omap3(cpu) \ 831 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 832 833 struct omap_mpu_state_s { 834 enum omap_mpu_model { 835 omap310, 836 omap1510, 837 omap1610, 838 omap1710, 839 omap2410, 840 omap2420, 841 omap2422, 842 omap2423, 843 omap2430, 844 omap3430, 845 omap3630, 846 } mpu_model; 847 848 ARMCPU *cpu; 849 850 qemu_irq *drq; 851 852 qemu_irq wakeup; 853 854 MemoryRegion ulpd_pm_iomem; 855 MemoryRegion pin_cfg_iomem; 856 MemoryRegion id_iomem; 857 MemoryRegion id_iomem_e18; 858 MemoryRegion id_iomem_ed4; 859 MemoryRegion id_iomem_e20; 860 MemoryRegion mpui_iomem; 861 MemoryRegion tcmi_iomem; 862 MemoryRegion clkm_iomem; 863 MemoryRegion clkdsp_iomem; 864 MemoryRegion mpui_io_iomem; 865 MemoryRegion tap_iomem; 866 MemoryRegion imif_ram; 867 MemoryRegion sram; 868 869 struct omap_dma_port_if_s { 870 uint32_t (*read[3])(struct omap_mpu_state_s *s, 871 hwaddr offset); 872 void (*write[3])(struct omap_mpu_state_s *s, 873 hwaddr offset, uint32_t value); 874 int (*addr_valid)(struct omap_mpu_state_s *s, 875 hwaddr addr); 876 } port[__omap_dma_port_last]; 877 878 uint64_t sdram_size; 879 unsigned long sram_size; 880 881 /* MPUI-TIPB peripherals */ 882 struct omap_uart_s *uart[3]; 883 884 DeviceState *gpio; 885 886 struct omap_mcbsp_s *mcbsp1; 887 struct omap_mcbsp_s *mcbsp3; 888 889 /* MPU public TIPB peripherals */ 890 struct omap_32khz_timer_s *os_timer; 891 892 struct omap_mmc_s *mmc; 893 894 struct omap_mpuio_s *mpuio; 895 896 struct omap_uwire_s *microwire; 897 898 struct omap_pwl_s *pwl; 899 struct omap_pwt_s *pwt; 900 DeviceState *i2c[2]; 901 902 struct omap_rtc_s *rtc; 903 904 struct omap_mcbsp_s *mcbsp2; 905 906 struct omap_lpg_s *led[2]; 907 908 /* MPU private TIPB peripherals */ 909 DeviceState *ih[2]; 910 911 struct soc_dma_s *dma; 912 913 struct omap_mpu_timer_s *timer[3]; 914 struct omap_watchdog_timer_s *wdt; 915 916 struct omap_lcd_panel_s *lcd; 917 918 uint32_t ulpd_pm_regs[21]; 919 int64_t ulpd_gauge_start; 920 921 uint32_t func_mux_ctrl[14]; 922 uint32_t comp_mode_ctrl[1]; 923 uint32_t pull_dwn_ctrl[4]; 924 uint32_t gate_inh_ctrl[1]; 925 uint32_t voltage_ctrl[1]; 926 uint32_t test_dbg_ctrl[1]; 927 uint32_t mod_conf_ctrl[1]; 928 int compat1509; 929 930 uint32_t mpui_ctrl; 931 932 struct omap_tipb_bridge_s *private_tipb; 933 struct omap_tipb_bridge_s *public_tipb; 934 935 uint32_t tcmi_regs[17]; 936 937 struct dpll_ctl_s *dpll[3]; 938 939 omap_clk clks; 940 struct { 941 int cold_start; 942 int clocking_scheme; 943 uint16_t arm_ckctl; 944 uint16_t arm_idlect1; 945 uint16_t arm_idlect2; 946 uint16_t arm_ewupct; 947 uint16_t arm_rstct1; 948 uint16_t arm_rstct2; 949 uint16_t arm_ckout1; 950 int dpll1_mode; 951 uint16_t dsp_idlect1; 952 uint16_t dsp_idlect2; 953 uint16_t dsp_rstct2; 954 } clkm; 955 956 /* OMAP2-only peripherals */ 957 struct omap_l4_s *l4; 958 959 struct omap_gp_timer_s *gptimer[12]; 960 struct omap_synctimer_s *synctimer; 961 962 struct omap_sdrc_s *sdrc; 963 struct omap_gpmc_s *gpmc; 964 965 struct omap_mcspi_s *mcspi[2]; 966 967 struct omap_dss_s *dss; 968 }; 969 970 /* omap1.c */ 971 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 972 const char *core); 973 974 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 975 void omap_badwidth_write8(void *opaque, hwaddr addr, 976 uint32_t value); 977 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 978 void omap_badwidth_write16(void *opaque, hwaddr addr, 979 uint32_t value); 980 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 981 void omap_badwidth_write32(void *opaque, hwaddr addr, 982 uint32_t value); 983 984 void omap_mpu_wakeup(void *opaque, int irq, int req); 985 986 # define OMAP_BAD_REG(paddr) \ 987 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 988 __func__, paddr) 989 # define OMAP_RO_REG(paddr) \ 990 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 991 HWADDR_PRIx "\n", \ 992 __func__, paddr) 993 994 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 995 * (Board-specific tags are not here) 996 */ 997 #define OMAP_TAG_CLOCK 0x4f01 998 #define OMAP_TAG_MMC 0x4f02 999 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1000 #define OMAP_TAG_USB 0x4f04 1001 #define OMAP_TAG_LCD 0x4f05 1002 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1003 #define OMAP_TAG_UART 0x4f07 1004 #define OMAP_TAG_FBMEM 0x4f08 1005 #define OMAP_TAG_STI_CONSOLE 0x4f09 1006 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1007 #define OMAP_TAG_PARTITION 0x4f0b 1008 #define OMAP_TAG_TEA5761 0x4f10 1009 #define OMAP_TAG_TMP105 0x4f11 1010 #define OMAP_TAG_BOOT_REASON 0x4f80 1011 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1012 #define OMAP_TAG_VERSION_STR 0x4f82 1013 1014 enum { 1015 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1016 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1017 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1018 }; 1019 1020 #define OMAP_GPIOSW_INVERTED 0x0001 1021 #define OMAP_GPIOSW_OUTPUT 0x0002 1022 1023 # define OMAP_MPUI_REG_MASK 0x000007ff 1024 1025 #endif 1026