1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "target/arm/cpu-qom.h" 25 #include "qemu/log.h" 26 #include "qom/object.h" 27 28 # define OMAP_EMIFS_BASE 0x00000000 29 # define OMAP2_Q0_BASE 0x00000000 30 # define OMAP_CS0_BASE 0x00000000 31 # define OMAP_CS1_BASE 0x04000000 32 # define OMAP_CS2_BASE 0x08000000 33 # define OMAP_CS3_BASE 0x0c000000 34 # define OMAP_EMIFF_BASE 0x10000000 35 # define OMAP_IMIF_BASE 0x20000000 36 # define OMAP_LOCALBUS_BASE 0x30000000 37 # define OMAP2_Q1_BASE 0x40000000 38 # define OMAP2_L4_BASE 0x48000000 39 # define OMAP2_SRAM_BASE 0x40200000 40 # define OMAP2_L3_BASE 0x68000000 41 # define OMAP2_Q2_BASE 0x80000000 42 # define OMAP2_Q3_BASE 0xc0000000 43 # define OMAP_MPUI_BASE 0xe1000000 44 45 # define OMAP730_SRAM_SIZE 0x00032000 46 # define OMAP15XX_SRAM_SIZE 0x00030000 47 # define OMAP16XX_SRAM_SIZE 0x00004000 48 # define OMAP1611_SRAM_SIZE 0x0003e800 49 # define OMAP242X_SRAM_SIZE 0x000a0000 50 # define OMAP243X_SRAM_SIZE 0x00010000 51 # define OMAP_CS0_SIZE 0x04000000 52 # define OMAP_CS1_SIZE 0x04000000 53 # define OMAP_CS2_SIZE 0x04000000 54 # define OMAP_CS3_SIZE 0x04000000 55 56 /* omap_clk.c */ 57 struct omap_mpu_state_s; 58 typedef struct clk *omap_clk; 59 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 60 void omap_clk_init(struct omap_mpu_state_s *mpu); 61 void omap_clk_adduser(struct clk *clk, qemu_irq user); 62 void omap_clk_get(omap_clk clk); 63 void omap_clk_put(omap_clk clk); 64 void omap_clk_onoff(omap_clk clk, int on); 65 void omap_clk_canidle(omap_clk clk, int can); 66 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 67 int64_t omap_clk_getrate(omap_clk clk); 68 void omap_clk_reparent(omap_clk clk, omap_clk parent); 69 70 /* omap_intc.c */ 71 #define TYPE_OMAP_INTC "common-omap-intc" 72 typedef struct OMAPIntcState OMAPIntcState; 73 DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) 74 75 76 /* 77 * TODO: Ideally we should have a clock framework that 78 * let us wire these clocks up with QOM properties or links. 79 * 80 * qdev should support a generic means of defining a 'port' with 81 * an arbitrary interface for connecting two devices. Then we 82 * could reframe the omap clock API in terms of clock ports, 83 * and get some type safety. For now the best qdev provides is 84 * passing an arbitrary pointer. 85 * (It's not possible to pass in the string which is the clock 86 * name, because this device does not have the necessary information 87 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 88 * translation.) 89 */ 90 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); 91 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); 92 93 /* omap_i2c.c */ 94 #define TYPE_OMAP_I2C "omap_i2c" 95 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 96 97 98 /* TODO: clock framework (see above) */ 99 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 100 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 101 102 /* omap_gpio.c */ 103 #define TYPE_OMAP1_GPIO "omap-gpio" 104 typedef struct Omap1GpioState Omap1GpioState; 105 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 106 TYPE_OMAP1_GPIO) 107 108 /* TODO: clock framework (see above) */ 109 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 110 111 /* 112 * Common IRQ numbers for level 1 interrupt handler 113 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 114 */ 115 # define OMAP_INT_CAMERA 1 116 # define OMAP_INT_FIQ 3 117 # define OMAP_INT_RTDX 6 118 # define OMAP_INT_DSP_MMU_ABORT 7 119 # define OMAP_INT_HOST 8 120 # define OMAP_INT_ABORT 9 121 # define OMAP_INT_BRIDGE_PRIV 13 122 # define OMAP_INT_GPIO_BANK1 14 123 # define OMAP_INT_UART3 15 124 # define OMAP_INT_TIMER3 16 125 # define OMAP_INT_DMA_CH0_6 19 126 # define OMAP_INT_DMA_CH1_7 20 127 # define OMAP_INT_DMA_CH2_8 21 128 # define OMAP_INT_DMA_CH3 22 129 # define OMAP_INT_DMA_CH4 23 130 # define OMAP_INT_DMA_CH5 24 131 # define OMAP_INT_DMA_LCD 25 132 # define OMAP_INT_TIMER1 26 133 # define OMAP_INT_WD_TIMER 27 134 # define OMAP_INT_BRIDGE_PUB 28 135 # define OMAP_INT_TIMER2 30 136 # define OMAP_INT_LCD_CTRL 31 137 138 /* 139 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 140 */ 141 # define OMAP_INT_15XX_IH2_IRQ 0 142 # define OMAP_INT_15XX_LB_MMU 17 143 # define OMAP_INT_15XX_LOCAL_BUS 29 144 145 /* 146 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 147 */ 148 # define OMAP_INT_1510_SPI_TX 4 149 # define OMAP_INT_1510_SPI_RX 5 150 # define OMAP_INT_1510_DSP_MAILBOX1 10 151 # define OMAP_INT_1510_DSP_MAILBOX2 11 152 153 /* 154 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 155 */ 156 # define OMAP_INT_310_McBSP2_TX 4 157 # define OMAP_INT_310_McBSP2_RX 5 158 # define OMAP_INT_310_HSB_MAILBOX1 12 159 # define OMAP_INT_310_HSAB_MMU 18 160 161 /* 162 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 163 */ 164 # define OMAP_INT_1610_IH2_IRQ 0 165 # define OMAP_INT_1610_IH2_FIQ 2 166 # define OMAP_INT_1610_McBSP2_TX 4 167 # define OMAP_INT_1610_McBSP2_RX 5 168 # define OMAP_INT_1610_DSP_MAILBOX1 10 169 # define OMAP_INT_1610_DSP_MAILBOX2 11 170 # define OMAP_INT_1610_LCD_LINE 12 171 # define OMAP_INT_1610_GPTIMER1 17 172 # define OMAP_INT_1610_GPTIMER2 18 173 # define OMAP_INT_1610_SSR_FIFO_0 29 174 175 /* 176 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 177 */ 178 # define OMAP_INT_730_IH2_FIQ 0 179 # define OMAP_INT_730_IH2_IRQ 1 180 # define OMAP_INT_730_USB_NON_ISO 2 181 # define OMAP_INT_730_USB_ISO 3 182 # define OMAP_INT_730_ICR 4 183 # define OMAP_INT_730_EAC 5 184 # define OMAP_INT_730_GPIO_BANK1 6 185 # define OMAP_INT_730_GPIO_BANK2 7 186 # define OMAP_INT_730_GPIO_BANK3 8 187 # define OMAP_INT_730_McBSP2TX 10 188 # define OMAP_INT_730_McBSP2RX 11 189 # define OMAP_INT_730_McBSP2RX_OVF 12 190 # define OMAP_INT_730_LCD_LINE 14 191 # define OMAP_INT_730_GSM_PROTECT 15 192 # define OMAP_INT_730_TIMER3 16 193 # define OMAP_INT_730_GPIO_BANK5 17 194 # define OMAP_INT_730_GPIO_BANK6 18 195 # define OMAP_INT_730_SPGIO_WR 29 196 197 /* 198 * Common IRQ numbers for level 2 interrupt handler 199 */ 200 # define OMAP_INT_KEYBOARD 1 201 # define OMAP_INT_uWireTX 2 202 # define OMAP_INT_uWireRX 3 203 # define OMAP_INT_I2C 4 204 # define OMAP_INT_MPUIO 5 205 # define OMAP_INT_USB_HHC_1 6 206 # define OMAP_INT_McBSP3TX 10 207 # define OMAP_INT_McBSP3RX 11 208 # define OMAP_INT_McBSP1TX 12 209 # define OMAP_INT_McBSP1RX 13 210 # define OMAP_INT_UART1 14 211 # define OMAP_INT_UART2 15 212 # define OMAP_INT_USB_W2FC 20 213 # define OMAP_INT_1WIRE 21 214 # define OMAP_INT_OS_TIMER 22 215 # define OMAP_INT_OQN 23 216 # define OMAP_INT_GAUGE_32K 24 217 # define OMAP_INT_RTC_TIMER 25 218 # define OMAP_INT_RTC_ALARM 26 219 # define OMAP_INT_DSP_MMU 28 220 221 /* 222 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 223 */ 224 # define OMAP_INT_1510_BT_MCSI1TX 16 225 # define OMAP_INT_1510_BT_MCSI1RX 17 226 # define OMAP_INT_1510_SoSSI_MATCH 19 227 # define OMAP_INT_1510_MEM_STICK 27 228 # define OMAP_INT_1510_COM_SPI_RO 31 229 230 /* 231 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 232 */ 233 # define OMAP_INT_310_FAC 0 234 # define OMAP_INT_310_USB_HHC_2 7 235 # define OMAP_INT_310_MCSI1_FE 16 236 # define OMAP_INT_310_MCSI2_FE 17 237 # define OMAP_INT_310_USB_W2FC_ISO 29 238 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 239 # define OMAP_INT_310_McBSP2RX_OF 31 240 241 /* 242 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 243 */ 244 # define OMAP_INT_1610_FAC 0 245 # define OMAP_INT_1610_USB_HHC_2 7 246 # define OMAP_INT_1610_USB_OTG 8 247 # define OMAP_INT_1610_SoSSI 9 248 # define OMAP_INT_1610_BT_MCSI1TX 16 249 # define OMAP_INT_1610_BT_MCSI1RX 17 250 # define OMAP_INT_1610_SoSSI_MATCH 19 251 # define OMAP_INT_1610_MEM_STICK 27 252 # define OMAP_INT_1610_McBSP2RX_OF 31 253 # define OMAP_INT_1610_STI 32 254 # define OMAP_INT_1610_STI_WAKEUP 33 255 # define OMAP_INT_1610_GPTIMER3 34 256 # define OMAP_INT_1610_GPTIMER4 35 257 # define OMAP_INT_1610_GPTIMER5 36 258 # define OMAP_INT_1610_GPTIMER6 37 259 # define OMAP_INT_1610_GPTIMER7 38 260 # define OMAP_INT_1610_GPTIMER8 39 261 # define OMAP_INT_1610_GPIO_BANK2 40 262 # define OMAP_INT_1610_GPIO_BANK3 41 263 # define OMAP_INT_1610_MMC2 42 264 # define OMAP_INT_1610_CF 43 265 # define OMAP_INT_1610_WAKE_UP_REQ 46 266 # define OMAP_INT_1610_GPIO_BANK4 48 267 # define OMAP_INT_1610_SPI 49 268 # define OMAP_INT_1610_DMA_CH6 53 269 # define OMAP_INT_1610_DMA_CH7 54 270 # define OMAP_INT_1610_DMA_CH8 55 271 # define OMAP_INT_1610_DMA_CH9 56 272 # define OMAP_INT_1610_DMA_CH10 57 273 # define OMAP_INT_1610_DMA_CH11 58 274 # define OMAP_INT_1610_DMA_CH12 59 275 # define OMAP_INT_1610_DMA_CH13 60 276 # define OMAP_INT_1610_DMA_CH14 61 277 # define OMAP_INT_1610_DMA_CH15 62 278 # define OMAP_INT_1610_NAND 63 279 280 /* 281 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 282 */ 283 # define OMAP_INT_730_HW_ERRORS 0 284 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 285 # define OMAP_INT_730_CFCD 2 286 # define OMAP_INT_730_CFIREQ 3 287 # define OMAP_INT_730_I2C 4 288 # define OMAP_INT_730_PCC 5 289 # define OMAP_INT_730_MPU_EXT_NIRQ 6 290 # define OMAP_INT_730_SPI_100K_1 7 291 # define OMAP_INT_730_SYREN_SPI 8 292 # define OMAP_INT_730_VLYNQ 9 293 # define OMAP_INT_730_GPIO_BANK4 10 294 # define OMAP_INT_730_McBSP1TX 11 295 # define OMAP_INT_730_McBSP1RX 12 296 # define OMAP_INT_730_McBSP1RX_OF 13 297 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 298 # define OMAP_INT_730_UART_MODEM_1 15 299 # define OMAP_INT_730_MCSI 16 300 # define OMAP_INT_730_uWireTX 17 301 # define OMAP_INT_730_uWireRX 18 302 # define OMAP_INT_730_SMC_CD 19 303 # define OMAP_INT_730_SMC_IREQ 20 304 # define OMAP_INT_730_HDQ_1WIRE 21 305 # define OMAP_INT_730_TIMER32K 22 306 # define OMAP_INT_730_MMC_SDIO 23 307 # define OMAP_INT_730_UPLD 24 308 # define OMAP_INT_730_USB_HHC_1 27 309 # define OMAP_INT_730_USB_HHC_2 28 310 # define OMAP_INT_730_USB_GENI 29 311 # define OMAP_INT_730_USB_OTG 30 312 # define OMAP_INT_730_CAMERA_IF 31 313 # define OMAP_INT_730_RNG 32 314 # define OMAP_INT_730_DUAL_MODE_TIMER 33 315 # define OMAP_INT_730_DBB_RF_EN 34 316 # define OMAP_INT_730_MPUIO_KEYPAD 35 317 # define OMAP_INT_730_SHA1_MD5 36 318 # define OMAP_INT_730_SPI_100K_2 37 319 # define OMAP_INT_730_RNG_IDLE 38 320 # define OMAP_INT_730_MPUIO 39 321 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 322 # define OMAP_INT_730_LLPC_OE_FALLING 41 323 # define OMAP_INT_730_LLPC_OE_RISING 42 324 # define OMAP_INT_730_LLPC_VSYNC 43 325 # define OMAP_INT_730_WAKE_UP_REQ 46 326 # define OMAP_INT_730_DMA_CH6 53 327 # define OMAP_INT_730_DMA_CH7 54 328 # define OMAP_INT_730_DMA_CH8 55 329 # define OMAP_INT_730_DMA_CH9 56 330 # define OMAP_INT_730_DMA_CH10 57 331 # define OMAP_INT_730_DMA_CH11 58 332 # define OMAP_INT_730_DMA_CH12 59 333 # define OMAP_INT_730_DMA_CH13 60 334 # define OMAP_INT_730_DMA_CH14 61 335 # define OMAP_INT_730_DMA_CH15 62 336 # define OMAP_INT_730_NAND 63 337 338 /* 339 * OMAP-24xx common IRQ numbers 340 */ 341 # define OMAP_INT_24XX_STI 4 342 # define OMAP_INT_24XX_SYS_NIRQ 7 343 # define OMAP_INT_24XX_L3_IRQ 10 344 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 345 # define OMAP_INT_24XX_SDMA_IRQ0 12 346 # define OMAP_INT_24XX_SDMA_IRQ1 13 347 # define OMAP_INT_24XX_SDMA_IRQ2 14 348 # define OMAP_INT_24XX_SDMA_IRQ3 15 349 # define OMAP_INT_243X_MCBSP2_IRQ 16 350 # define OMAP_INT_243X_MCBSP3_IRQ 17 351 # define OMAP_INT_243X_MCBSP4_IRQ 18 352 # define OMAP_INT_243X_MCBSP5_IRQ 19 353 # define OMAP_INT_24XX_GPMC_IRQ 20 354 # define OMAP_INT_24XX_GUFFAW_IRQ 21 355 # define OMAP_INT_24XX_IVA_IRQ 22 356 # define OMAP_INT_24XX_EAC_IRQ 23 357 # define OMAP_INT_24XX_CAM_IRQ 24 358 # define OMAP_INT_24XX_DSS_IRQ 25 359 # define OMAP_INT_24XX_MAIL_U0_MPU 26 360 # define OMAP_INT_24XX_DSP_UMA 27 361 # define OMAP_INT_24XX_DSP_MMU 28 362 # define OMAP_INT_24XX_GPIO_BANK1 29 363 # define OMAP_INT_24XX_GPIO_BANK2 30 364 # define OMAP_INT_24XX_GPIO_BANK3 31 365 # define OMAP_INT_24XX_GPIO_BANK4 32 366 # define OMAP_INT_243X_GPIO_BANK5 33 367 # define OMAP_INT_24XX_MAIL_U3_MPU 34 368 # define OMAP_INT_24XX_WDT3 35 369 # define OMAP_INT_24XX_WDT4 36 370 # define OMAP_INT_24XX_GPTIMER1 37 371 # define OMAP_INT_24XX_GPTIMER2 38 372 # define OMAP_INT_24XX_GPTIMER3 39 373 # define OMAP_INT_24XX_GPTIMER4 40 374 # define OMAP_INT_24XX_GPTIMER5 41 375 # define OMAP_INT_24XX_GPTIMER6 42 376 # define OMAP_INT_24XX_GPTIMER7 43 377 # define OMAP_INT_24XX_GPTIMER8 44 378 # define OMAP_INT_24XX_GPTIMER9 45 379 # define OMAP_INT_24XX_GPTIMER10 46 380 # define OMAP_INT_24XX_GPTIMER11 47 381 # define OMAP_INT_24XX_GPTIMER12 48 382 # define OMAP_INT_24XX_PKA_IRQ 50 383 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 384 # define OMAP_INT_24XX_RNG_IRQ 52 385 # define OMAP_INT_24XX_MG_IRQ 53 386 # define OMAP_INT_24XX_I2C1_IRQ 56 387 # define OMAP_INT_24XX_I2C2_IRQ 57 388 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 389 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 390 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 391 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 392 # define OMAP_INT_243X_MCBSP1_IRQ 64 393 # define OMAP_INT_24XX_MCSPI1_IRQ 65 394 # define OMAP_INT_24XX_MCSPI2_IRQ 66 395 # define OMAP_INT_24XX_SSI1_IRQ0 67 396 # define OMAP_INT_24XX_SSI1_IRQ1 68 397 # define OMAP_INT_24XX_SSI2_IRQ0 69 398 # define OMAP_INT_24XX_SSI2_IRQ1 70 399 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 400 # define OMAP_INT_24XX_UART1_IRQ 72 401 # define OMAP_INT_24XX_UART2_IRQ 73 402 # define OMAP_INT_24XX_UART3_IRQ 74 403 # define OMAP_INT_24XX_USB_IRQ_GEN 75 404 # define OMAP_INT_24XX_USB_IRQ_NISO 76 405 # define OMAP_INT_24XX_USB_IRQ_ISO 77 406 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 407 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 408 # define OMAP_INT_24XX_USB_IRQ_OTG 80 409 # define OMAP_INT_24XX_VLYNQ_IRQ 81 410 # define OMAP_INT_24XX_MMC_IRQ 83 411 # define OMAP_INT_24XX_MS_IRQ 84 412 # define OMAP_INT_24XX_FAC_IRQ 85 413 # define OMAP_INT_24XX_MCSPI3_IRQ 91 414 # define OMAP_INT_243X_HS_USB_MC 92 415 # define OMAP_INT_243X_HS_USB_DMA 93 416 # define OMAP_INT_243X_CARKIT 94 417 # define OMAP_INT_34XX_GPTIMER12 95 418 419 /* omap_dma.c */ 420 enum omap_dma_model { 421 omap_dma_3_0, 422 omap_dma_3_1, 423 omap_dma_3_2, 424 }; 425 426 struct soc_dma_s; 427 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 428 MemoryRegion *sysmem, 429 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 430 enum omap_dma_model model); 431 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 432 MemoryRegion *sysmem, 433 struct omap_mpu_state_s *mpu, int fifo, 434 int chans, omap_clk iclk, omap_clk fclk); 435 void omap_dma_reset(struct soc_dma_s *s); 436 437 struct dma_irq_map { 438 int ih; 439 int intr; 440 }; 441 442 /* Only used in OMAP DMA 3.x gigacells */ 443 enum omap_dma_port { 444 emiff = 0, 445 emifs, 446 imif, /* omap16xx: ocp_t1 */ 447 tipb, 448 local, /* omap16xx: ocp_t2 */ 449 tipb_mpui, 450 __omap_dma_port_last, 451 }; 452 453 typedef enum { 454 constant = 0, 455 post_incremented, 456 single_index, 457 double_index, 458 } omap_dma_addressing_t; 459 460 /* Only used in OMAP DMA 3.x gigacells */ 461 struct omap_dma_lcd_channel_s { 462 enum omap_dma_port src; 463 hwaddr src_f1_top; 464 hwaddr src_f1_bottom; 465 hwaddr src_f2_top; 466 hwaddr src_f2_bottom; 467 468 /* Used in OMAP DMA 3.2 gigacell */ 469 unsigned char brust_f1; 470 unsigned char pack_f1; 471 unsigned char data_type_f1; 472 unsigned char brust_f2; 473 unsigned char pack_f2; 474 unsigned char data_type_f2; 475 unsigned char end_prog; 476 unsigned char repeat; 477 unsigned char auto_init; 478 unsigned char priority; 479 unsigned char fs; 480 unsigned char running; 481 unsigned char bs; 482 unsigned char omap_3_1_compatible_disable; 483 unsigned char dst; 484 unsigned char lch_type; 485 int16_t element_index_f1; 486 int16_t element_index_f2; 487 int32_t frame_index_f1; 488 int32_t frame_index_f2; 489 uint16_t elements_f1; 490 uint16_t frames_f1; 491 uint16_t elements_f2; 492 uint16_t frames_f2; 493 omap_dma_addressing_t mode_f1; 494 omap_dma_addressing_t mode_f2; 495 496 /* Destination port is fixed. */ 497 int interrupts; 498 int condition; 499 int dual; 500 501 int current_frame; 502 hwaddr phys_framebuffer[2]; 503 qemu_irq irq; 504 struct omap_mpu_state_s *mpu; 505 } *omap_dma_get_lcdch(struct soc_dma_s *s); 506 507 /* 508 * DMA request numbers for OMAP1 509 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 510 */ 511 # define OMAP_DMA_NO_DEVICE 0 512 # define OMAP_DMA_MCSI1_TX 1 513 # define OMAP_DMA_MCSI1_RX 2 514 # define OMAP_DMA_I2C_RX 3 515 # define OMAP_DMA_I2C_TX 4 516 # define OMAP_DMA_EXT_NDMA_REQ0 5 517 # define OMAP_DMA_EXT_NDMA_REQ1 6 518 # define OMAP_DMA_UWIRE_TX 7 519 # define OMAP_DMA_MCBSP1_TX 8 520 # define OMAP_DMA_MCBSP1_RX 9 521 # define OMAP_DMA_MCBSP3_TX 10 522 # define OMAP_DMA_MCBSP3_RX 11 523 # define OMAP_DMA_UART1_TX 12 524 # define OMAP_DMA_UART1_RX 13 525 # define OMAP_DMA_UART2_TX 14 526 # define OMAP_DMA_UART2_RX 15 527 # define OMAP_DMA_MCBSP2_TX 16 528 # define OMAP_DMA_MCBSP2_RX 17 529 # define OMAP_DMA_UART3_TX 18 530 # define OMAP_DMA_UART3_RX 19 531 # define OMAP_DMA_CAMERA_IF_RX 20 532 # define OMAP_DMA_MMC_TX 21 533 # define OMAP_DMA_MMC_RX 22 534 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 535 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 536 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 537 # define OMAP_DMA_USB_W2FC_RX0 26 538 # define OMAP_DMA_USB_W2FC_RX1 27 539 # define OMAP_DMA_USB_W2FC_RX2 28 540 # define OMAP_DMA_USB_W2FC_TX0 29 541 # define OMAP_DMA_USB_W2FC_TX1 30 542 # define OMAP_DMA_USB_W2FC_TX2 31 543 544 /* These are only for 1610 */ 545 # define OMAP_DMA_CRYPTO_DES_IN 32 546 # define OMAP_DMA_SPI_TX 33 547 # define OMAP_DMA_SPI_RX 34 548 # define OMAP_DMA_CRYPTO_HASH 35 549 # define OMAP_DMA_CCP_ATTN 36 550 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 551 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 552 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 553 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 554 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 555 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 556 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 557 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 558 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 559 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 560 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 561 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 562 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 563 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 564 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 565 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 566 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 567 # define OMAP_DMA_MMC2_TX 54 568 # define OMAP_DMA_MMC2_RX 55 569 # define OMAP_DMA_CRYPTO_DES_OUT 56 570 571 /* 572 * DMA request numbers for the OMAP2 573 */ 574 # define OMAP24XX_DMA_NO_DEVICE 0 575 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 576 # define OMAP24XX_DMA_EXT_DMAREQ0 2 577 # define OMAP24XX_DMA_EXT_DMAREQ1 3 578 # define OMAP24XX_DMA_GPMC 4 579 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 580 # define OMAP24XX_DMA_DSS 6 581 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 582 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 583 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 584 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 585 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 586 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 587 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 588 # define OMAP24XX_DMA_EXT_DMAREQ2 14 589 # define OMAP24XX_DMA_EXT_DMAREQ3 15 590 # define OMAP24XX_DMA_EXT_DMAREQ4 16 591 # define OMAP24XX_DMA_EAC_AC_RD 17 592 # define OMAP24XX_DMA_EAC_AC_WR 18 593 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 594 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 595 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 596 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 597 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 598 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 599 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 600 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 601 # define OMAP24XX_DMA_I2C1_TX 27 602 # define OMAP24XX_DMA_I2C1_RX 28 603 # define OMAP24XX_DMA_I2C2_TX 29 604 # define OMAP24XX_DMA_I2C2_RX 30 605 # define OMAP24XX_DMA_MCBSP1_TX 31 606 # define OMAP24XX_DMA_MCBSP1_RX 32 607 # define OMAP24XX_DMA_MCBSP2_TX 33 608 # define OMAP24XX_DMA_MCBSP2_RX 34 609 # define OMAP24XX_DMA_SPI1_TX0 35 610 # define OMAP24XX_DMA_SPI1_RX0 36 611 # define OMAP24XX_DMA_SPI1_TX1 37 612 # define OMAP24XX_DMA_SPI1_RX1 38 613 # define OMAP24XX_DMA_SPI1_TX2 39 614 # define OMAP24XX_DMA_SPI1_RX2 40 615 # define OMAP24XX_DMA_SPI1_TX3 41 616 # define OMAP24XX_DMA_SPI1_RX3 42 617 # define OMAP24XX_DMA_SPI2_TX0 43 618 # define OMAP24XX_DMA_SPI2_RX0 44 619 # define OMAP24XX_DMA_SPI2_TX1 45 620 # define OMAP24XX_DMA_SPI2_RX1 46 621 622 # define OMAP24XX_DMA_UART1_TX 49 623 # define OMAP24XX_DMA_UART1_RX 50 624 # define OMAP24XX_DMA_UART2_TX 51 625 # define OMAP24XX_DMA_UART2_RX 52 626 # define OMAP24XX_DMA_UART3_TX 53 627 # define OMAP24XX_DMA_UART3_RX 54 628 # define OMAP24XX_DMA_USB_W2FC_TX0 55 629 # define OMAP24XX_DMA_USB_W2FC_RX0 56 630 # define OMAP24XX_DMA_USB_W2FC_TX1 57 631 # define OMAP24XX_DMA_USB_W2FC_RX1 58 632 # define OMAP24XX_DMA_USB_W2FC_TX2 59 633 # define OMAP24XX_DMA_USB_W2FC_RX2 60 634 # define OMAP24XX_DMA_MMC1_TX 61 635 # define OMAP24XX_DMA_MMC1_RX 62 636 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 637 # define OMAP24XX_DMA_EXT_DMAREQ5 64 638 639 struct omap_uart_s; 640 struct omap_uart_s *omap_uart_init(hwaddr base, 641 qemu_irq irq, omap_clk fclk, omap_clk iclk, 642 qemu_irq txdma, qemu_irq rxdma, 643 const char *label, Chardev *chr); 644 void omap_uart_reset(struct omap_uart_s *s); 645 646 struct omap_mpuio_s; 647 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 648 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 649 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 650 651 typedef struct uWireSlave { 652 uint16_t (*receive)(void *opaque); 653 void (*send)(void *opaque, uint16_t data); 654 void *opaque; 655 } uWireSlave; 656 657 struct omap_uwire_s; 658 void omap_uwire_attach(struct omap_uwire_s *s, 659 uWireSlave *slave, int chipselect); 660 661 struct I2SCodec { 662 void *opaque; 663 664 /* The CPU can call this if it is generating the clock signal on the 665 * i2s port. The CODEC can ignore it if it is set up as a clock 666 * master and generates its own clock. */ 667 void (*set_rate)(void *opaque, int in, int out); 668 669 void (*tx_swallow)(void *opaque); 670 qemu_irq rx_swallow; 671 qemu_irq tx_start; 672 673 int tx_rate; 674 int cts; 675 int rx_rate; 676 int rts; 677 678 struct i2s_fifo_s { 679 uint8_t *fifo; 680 int len; 681 int start; 682 int size; 683 } in, out; 684 }; 685 struct omap_mcbsp_s; 686 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 687 688 /* omap_lcdc.c */ 689 struct omap_lcd_panel_s; 690 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 691 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 692 hwaddr base, 693 qemu_irq irq, 694 struct omap_dma_lcd_channel_s *dma, 695 omap_clk clk); 696 697 /* omap_mmc.c */ 698 struct omap_mmc_s; 699 struct omap_mmc_s *omap_mmc_init(hwaddr base, 700 MemoryRegion *sysmem, 701 BlockBackend *blk, 702 qemu_irq irq, qemu_irq dma[], omap_clk clk); 703 void omap_mmc_reset(struct omap_mmc_s *s); 704 705 /* omap_i2c.c */ 706 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 707 708 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 709 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 710 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 711 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 712 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 713 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 714 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 715 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 716 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 717 718 # define cpu_is_omap15xx(cpu) \ 719 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 720 # define cpu_is_omap16xx(cpu) \ 721 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 722 # define cpu_is_omap24xx(cpu) \ 723 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 724 725 # define cpu_class_omap1(cpu) \ 726 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 727 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 728 # define cpu_class_omap3(cpu) \ 729 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 730 731 struct omap_mpu_state_s { 732 enum omap_mpu_model { 733 omap310, 734 omap1510, 735 omap1610, 736 omap1710, 737 omap2410, 738 omap2420, 739 omap2422, 740 omap2423, 741 omap2430, 742 omap3430, 743 omap3630, 744 } mpu_model; 745 746 ARMCPU *cpu; 747 748 qemu_irq *drq; 749 750 qemu_irq wakeup; 751 752 MemoryRegion ulpd_pm_iomem; 753 MemoryRegion pin_cfg_iomem; 754 MemoryRegion id_iomem; 755 MemoryRegion id_iomem_e18; 756 MemoryRegion id_iomem_ed4; 757 MemoryRegion id_iomem_e20; 758 MemoryRegion mpui_iomem; 759 MemoryRegion tcmi_iomem; 760 MemoryRegion clkm_iomem; 761 MemoryRegion clkdsp_iomem; 762 MemoryRegion mpui_io_iomem; 763 MemoryRegion tap_iomem; 764 MemoryRegion imif_ram; 765 MemoryRegion sram; 766 767 struct omap_dma_port_if_s { 768 uint32_t (*read[3])(struct omap_mpu_state_s *s, 769 hwaddr offset); 770 void (*write[3])(struct omap_mpu_state_s *s, 771 hwaddr offset, uint32_t value); 772 int (*addr_valid)(struct omap_mpu_state_s *s, 773 hwaddr addr); 774 } port[__omap_dma_port_last]; 775 776 uint64_t sdram_size; 777 unsigned long sram_size; 778 779 /* MPUI-TIPB peripherals */ 780 struct omap_uart_s *uart[3]; 781 782 DeviceState *gpio; 783 784 struct omap_mcbsp_s *mcbsp1; 785 struct omap_mcbsp_s *mcbsp3; 786 787 /* MPU public TIPB peripherals */ 788 struct omap_32khz_timer_s *os_timer; 789 790 struct omap_mmc_s *mmc; 791 792 struct omap_mpuio_s *mpuio; 793 794 struct omap_uwire_s *microwire; 795 796 struct omap_pwl_s *pwl; 797 struct omap_pwt_s *pwt; 798 DeviceState *i2c[2]; 799 800 struct omap_rtc_s *rtc; 801 802 struct omap_mcbsp_s *mcbsp2; 803 804 struct omap_lpg_s *led[2]; 805 806 /* MPU private TIPB peripherals */ 807 DeviceState *ih[2]; 808 809 struct soc_dma_s *dma; 810 811 struct omap_mpu_timer_s *timer[3]; 812 struct omap_watchdog_timer_s *wdt; 813 814 struct omap_lcd_panel_s *lcd; 815 816 uint32_t ulpd_pm_regs[21]; 817 int64_t ulpd_gauge_start; 818 819 uint32_t func_mux_ctrl[14]; 820 uint32_t comp_mode_ctrl[1]; 821 uint32_t pull_dwn_ctrl[4]; 822 uint32_t gate_inh_ctrl[1]; 823 uint32_t voltage_ctrl[1]; 824 uint32_t test_dbg_ctrl[1]; 825 uint32_t mod_conf_ctrl[1]; 826 int compat1509; 827 828 uint32_t mpui_ctrl; 829 830 struct omap_tipb_bridge_s *private_tipb; 831 struct omap_tipb_bridge_s *public_tipb; 832 833 uint32_t tcmi_regs[17]; 834 835 struct dpll_ctl_s *dpll[3]; 836 837 omap_clk clks; 838 struct { 839 int cold_start; 840 int clocking_scheme; 841 uint16_t arm_ckctl; 842 uint16_t arm_idlect1; 843 uint16_t arm_idlect2; 844 uint16_t arm_ewupct; 845 uint16_t arm_rstct1; 846 uint16_t arm_rstct2; 847 uint16_t arm_ckout1; 848 int dpll1_mode; 849 uint16_t dsp_idlect1; 850 uint16_t dsp_idlect2; 851 uint16_t dsp_rstct2; 852 } clkm; 853 }; 854 855 /* omap1.c */ 856 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 857 const char *core); 858 859 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 860 void omap_badwidth_write8(void *opaque, hwaddr addr, 861 uint32_t value); 862 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 863 void omap_badwidth_write16(void *opaque, hwaddr addr, 864 uint32_t value); 865 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 866 void omap_badwidth_write32(void *opaque, hwaddr addr, 867 uint32_t value); 868 869 void omap_mpu_wakeup(void *opaque, int irq, int req); 870 871 # define OMAP_BAD_REG(paddr) \ 872 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 873 __func__, paddr) 874 # define OMAP_RO_REG(paddr) \ 875 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 876 HWADDR_PRIx "\n", \ 877 __func__, paddr) 878 879 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 880 * (Board-specific tags are not here) 881 */ 882 #define OMAP_TAG_CLOCK 0x4f01 883 #define OMAP_TAG_MMC 0x4f02 884 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 885 #define OMAP_TAG_USB 0x4f04 886 #define OMAP_TAG_LCD 0x4f05 887 #define OMAP_TAG_GPIO_SWITCH 0x4f06 888 #define OMAP_TAG_UART 0x4f07 889 #define OMAP_TAG_FBMEM 0x4f08 890 #define OMAP_TAG_STI_CONSOLE 0x4f09 891 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 892 #define OMAP_TAG_PARTITION 0x4f0b 893 #define OMAP_TAG_TEA5761 0x4f10 894 #define OMAP_TAG_TMP105 0x4f11 895 #define OMAP_TAG_BOOT_REASON 0x4f80 896 #define OMAP_TAG_FLASH_PART_STR 0x4f81 897 #define OMAP_TAG_VERSION_STR 0x4f82 898 899 enum { 900 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 901 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 902 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 903 }; 904 905 #define OMAP_GPIOSW_INVERTED 0x0001 906 #define OMAP_GPIOSW_OUTPUT 0x0002 907 908 # define OMAP_MPUI_REG_MASK 0x000007ff 909 910 #endif 911