1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "hw/input/tsc2xxx.h" 25 #include "target/arm/cpu-qom.h" 26 #include "qemu/log.h" 27 28 # define OMAP_EMIFS_BASE 0x00000000 29 # define OMAP2_Q0_BASE 0x00000000 30 # define OMAP_CS0_BASE 0x00000000 31 # define OMAP_CS1_BASE 0x04000000 32 # define OMAP_CS2_BASE 0x08000000 33 # define OMAP_CS3_BASE 0x0c000000 34 # define OMAP_EMIFF_BASE 0x10000000 35 # define OMAP_IMIF_BASE 0x20000000 36 # define OMAP_LOCALBUS_BASE 0x30000000 37 # define OMAP2_Q1_BASE 0x40000000 38 # define OMAP2_L4_BASE 0x48000000 39 # define OMAP2_SRAM_BASE 0x40200000 40 # define OMAP2_L3_BASE 0x68000000 41 # define OMAP2_Q2_BASE 0x80000000 42 # define OMAP2_Q3_BASE 0xc0000000 43 # define OMAP_MPUI_BASE 0xe1000000 44 45 # define OMAP730_SRAM_SIZE 0x00032000 46 # define OMAP15XX_SRAM_SIZE 0x00030000 47 # define OMAP16XX_SRAM_SIZE 0x00004000 48 # define OMAP1611_SRAM_SIZE 0x0003e800 49 # define OMAP242X_SRAM_SIZE 0x000a0000 50 # define OMAP243X_SRAM_SIZE 0x00010000 51 # define OMAP_CS0_SIZE 0x04000000 52 # define OMAP_CS1_SIZE 0x04000000 53 # define OMAP_CS2_SIZE 0x04000000 54 # define OMAP_CS3_SIZE 0x04000000 55 56 /* omap_clk.c */ 57 struct omap_mpu_state_s; 58 typedef struct clk *omap_clk; 59 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 60 void omap_clk_init(struct omap_mpu_state_s *mpu); 61 void omap_clk_adduser(struct clk *clk, qemu_irq user); 62 void omap_clk_get(omap_clk clk); 63 void omap_clk_put(omap_clk clk); 64 void omap_clk_onoff(omap_clk clk, int on); 65 void omap_clk_canidle(omap_clk clk, int can); 66 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 67 int64_t omap_clk_getrate(omap_clk clk); 68 void omap_clk_reparent(omap_clk clk, omap_clk parent); 69 70 /* omap_intc.c */ 71 #define TYPE_OMAP_INTC "common-omap-intc" 72 #define OMAP_INTC(obj) \ 73 OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC) 74 75 typedef struct omap_intr_handler_s omap_intr_handler; 76 77 /* 78 * TODO: Ideally we should have a clock framework that 79 * let us wire these clocks up with QOM properties or links. 80 */ 81 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); 82 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); 83 84 /* omap_i2c.c */ 85 #define TYPE_OMAP_I2C "omap_i2c" 86 #define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) 87 88 typedef struct OMAPI2CState OMAPI2CState; 89 90 /* 91 * TODO: Ideally we should have a clock framework that 92 * let us wire these clocks up with QOM properties or links. 93 */ 94 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 95 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 96 97 /* OMAP2 l4 Interconnect */ 98 struct omap_l4_s; 99 struct omap_l4_region_s { 100 hwaddr offset; 101 size_t size; 102 int access; 103 }; 104 struct omap_l4_agent_info_s { 105 int ta; 106 int region; 107 int regions; 108 int ta_region; 109 }; 110 struct omap_target_agent_s { 111 MemoryRegion iomem; 112 struct omap_l4_s *bus; 113 int regions; 114 const struct omap_l4_region_s *start; 115 hwaddr base; 116 uint32_t component; 117 uint32_t control; 118 uint32_t status; 119 }; 120 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 121 hwaddr base, int ta_num); 122 123 struct omap_target_agent_s; 124 struct omap_target_agent_s *omap_l4ta_get( 125 struct omap_l4_s *bus, 126 const struct omap_l4_region_s *regions, 127 const struct omap_l4_agent_info_s *agents, 128 int cs); 129 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 130 int region, MemoryRegion *mr); 131 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 132 int region); 133 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 134 int region); 135 136 /* OMAP2 SDRAM controller */ 137 struct omap_sdrc_s; 138 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 139 hwaddr base); 140 void omap_sdrc_reset(struct omap_sdrc_s *s); 141 142 /* OMAP2 general purpose memory controller */ 143 struct omap_gpmc_s; 144 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 145 hwaddr base, 146 qemu_irq irq, qemu_irq drq); 147 void omap_gpmc_reset(struct omap_gpmc_s *s); 148 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 149 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 150 151 /* 152 * Common IRQ numbers for level 1 interrupt handler 153 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 154 */ 155 # define OMAP_INT_CAMERA 1 156 # define OMAP_INT_FIQ 3 157 # define OMAP_INT_RTDX 6 158 # define OMAP_INT_DSP_MMU_ABORT 7 159 # define OMAP_INT_HOST 8 160 # define OMAP_INT_ABORT 9 161 # define OMAP_INT_BRIDGE_PRIV 13 162 # define OMAP_INT_GPIO_BANK1 14 163 # define OMAP_INT_UART3 15 164 # define OMAP_INT_TIMER3 16 165 # define OMAP_INT_DMA_CH0_6 19 166 # define OMAP_INT_DMA_CH1_7 20 167 # define OMAP_INT_DMA_CH2_8 21 168 # define OMAP_INT_DMA_CH3 22 169 # define OMAP_INT_DMA_CH4 23 170 # define OMAP_INT_DMA_CH5 24 171 # define OMAP_INT_DMA_LCD 25 172 # define OMAP_INT_TIMER1 26 173 # define OMAP_INT_WD_TIMER 27 174 # define OMAP_INT_BRIDGE_PUB 28 175 # define OMAP_INT_TIMER2 30 176 # define OMAP_INT_LCD_CTRL 31 177 178 /* 179 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 180 */ 181 # define OMAP_INT_15XX_IH2_IRQ 0 182 # define OMAP_INT_15XX_LB_MMU 17 183 # define OMAP_INT_15XX_LOCAL_BUS 29 184 185 /* 186 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 187 */ 188 # define OMAP_INT_1510_SPI_TX 4 189 # define OMAP_INT_1510_SPI_RX 5 190 # define OMAP_INT_1510_DSP_MAILBOX1 10 191 # define OMAP_INT_1510_DSP_MAILBOX2 11 192 193 /* 194 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 195 */ 196 # define OMAP_INT_310_McBSP2_TX 4 197 # define OMAP_INT_310_McBSP2_RX 5 198 # define OMAP_INT_310_HSB_MAILBOX1 12 199 # define OMAP_INT_310_HSAB_MMU 18 200 201 /* 202 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 203 */ 204 # define OMAP_INT_1610_IH2_IRQ 0 205 # define OMAP_INT_1610_IH2_FIQ 2 206 # define OMAP_INT_1610_McBSP2_TX 4 207 # define OMAP_INT_1610_McBSP2_RX 5 208 # define OMAP_INT_1610_DSP_MAILBOX1 10 209 # define OMAP_INT_1610_DSP_MAILBOX2 11 210 # define OMAP_INT_1610_LCD_LINE 12 211 # define OMAP_INT_1610_GPTIMER1 17 212 # define OMAP_INT_1610_GPTIMER2 18 213 # define OMAP_INT_1610_SSR_FIFO_0 29 214 215 /* 216 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 217 */ 218 # define OMAP_INT_730_IH2_FIQ 0 219 # define OMAP_INT_730_IH2_IRQ 1 220 # define OMAP_INT_730_USB_NON_ISO 2 221 # define OMAP_INT_730_USB_ISO 3 222 # define OMAP_INT_730_ICR 4 223 # define OMAP_INT_730_EAC 5 224 # define OMAP_INT_730_GPIO_BANK1 6 225 # define OMAP_INT_730_GPIO_BANK2 7 226 # define OMAP_INT_730_GPIO_BANK3 8 227 # define OMAP_INT_730_McBSP2TX 10 228 # define OMAP_INT_730_McBSP2RX 11 229 # define OMAP_INT_730_McBSP2RX_OVF 12 230 # define OMAP_INT_730_LCD_LINE 14 231 # define OMAP_INT_730_GSM_PROTECT 15 232 # define OMAP_INT_730_TIMER3 16 233 # define OMAP_INT_730_GPIO_BANK5 17 234 # define OMAP_INT_730_GPIO_BANK6 18 235 # define OMAP_INT_730_SPGIO_WR 29 236 237 /* 238 * Common IRQ numbers for level 2 interrupt handler 239 */ 240 # define OMAP_INT_KEYBOARD 1 241 # define OMAP_INT_uWireTX 2 242 # define OMAP_INT_uWireRX 3 243 # define OMAP_INT_I2C 4 244 # define OMAP_INT_MPUIO 5 245 # define OMAP_INT_USB_HHC_1 6 246 # define OMAP_INT_McBSP3TX 10 247 # define OMAP_INT_McBSP3RX 11 248 # define OMAP_INT_McBSP1TX 12 249 # define OMAP_INT_McBSP1RX 13 250 # define OMAP_INT_UART1 14 251 # define OMAP_INT_UART2 15 252 # define OMAP_INT_USB_W2FC 20 253 # define OMAP_INT_1WIRE 21 254 # define OMAP_INT_OS_TIMER 22 255 # define OMAP_INT_OQN 23 256 # define OMAP_INT_GAUGE_32K 24 257 # define OMAP_INT_RTC_TIMER 25 258 # define OMAP_INT_RTC_ALARM 26 259 # define OMAP_INT_DSP_MMU 28 260 261 /* 262 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 263 */ 264 # define OMAP_INT_1510_BT_MCSI1TX 16 265 # define OMAP_INT_1510_BT_MCSI1RX 17 266 # define OMAP_INT_1510_SoSSI_MATCH 19 267 # define OMAP_INT_1510_MEM_STICK 27 268 # define OMAP_INT_1510_COM_SPI_RO 31 269 270 /* 271 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 272 */ 273 # define OMAP_INT_310_FAC 0 274 # define OMAP_INT_310_USB_HHC_2 7 275 # define OMAP_INT_310_MCSI1_FE 16 276 # define OMAP_INT_310_MCSI2_FE 17 277 # define OMAP_INT_310_USB_W2FC_ISO 29 278 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 279 # define OMAP_INT_310_McBSP2RX_OF 31 280 281 /* 282 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 283 */ 284 # define OMAP_INT_1610_FAC 0 285 # define OMAP_INT_1610_USB_HHC_2 7 286 # define OMAP_INT_1610_USB_OTG 8 287 # define OMAP_INT_1610_SoSSI 9 288 # define OMAP_INT_1610_BT_MCSI1TX 16 289 # define OMAP_INT_1610_BT_MCSI1RX 17 290 # define OMAP_INT_1610_SoSSI_MATCH 19 291 # define OMAP_INT_1610_MEM_STICK 27 292 # define OMAP_INT_1610_McBSP2RX_OF 31 293 # define OMAP_INT_1610_STI 32 294 # define OMAP_INT_1610_STI_WAKEUP 33 295 # define OMAP_INT_1610_GPTIMER3 34 296 # define OMAP_INT_1610_GPTIMER4 35 297 # define OMAP_INT_1610_GPTIMER5 36 298 # define OMAP_INT_1610_GPTIMER6 37 299 # define OMAP_INT_1610_GPTIMER7 38 300 # define OMAP_INT_1610_GPTIMER8 39 301 # define OMAP_INT_1610_GPIO_BANK2 40 302 # define OMAP_INT_1610_GPIO_BANK3 41 303 # define OMAP_INT_1610_MMC2 42 304 # define OMAP_INT_1610_CF 43 305 # define OMAP_INT_1610_WAKE_UP_REQ 46 306 # define OMAP_INT_1610_GPIO_BANK4 48 307 # define OMAP_INT_1610_SPI 49 308 # define OMAP_INT_1610_DMA_CH6 53 309 # define OMAP_INT_1610_DMA_CH7 54 310 # define OMAP_INT_1610_DMA_CH8 55 311 # define OMAP_INT_1610_DMA_CH9 56 312 # define OMAP_INT_1610_DMA_CH10 57 313 # define OMAP_INT_1610_DMA_CH11 58 314 # define OMAP_INT_1610_DMA_CH12 59 315 # define OMAP_INT_1610_DMA_CH13 60 316 # define OMAP_INT_1610_DMA_CH14 61 317 # define OMAP_INT_1610_DMA_CH15 62 318 # define OMAP_INT_1610_NAND 63 319 320 /* 321 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 322 */ 323 # define OMAP_INT_730_HW_ERRORS 0 324 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 325 # define OMAP_INT_730_CFCD 2 326 # define OMAP_INT_730_CFIREQ 3 327 # define OMAP_INT_730_I2C 4 328 # define OMAP_INT_730_PCC 5 329 # define OMAP_INT_730_MPU_EXT_NIRQ 6 330 # define OMAP_INT_730_SPI_100K_1 7 331 # define OMAP_INT_730_SYREN_SPI 8 332 # define OMAP_INT_730_VLYNQ 9 333 # define OMAP_INT_730_GPIO_BANK4 10 334 # define OMAP_INT_730_McBSP1TX 11 335 # define OMAP_INT_730_McBSP1RX 12 336 # define OMAP_INT_730_McBSP1RX_OF 13 337 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 338 # define OMAP_INT_730_UART_MODEM_1 15 339 # define OMAP_INT_730_MCSI 16 340 # define OMAP_INT_730_uWireTX 17 341 # define OMAP_INT_730_uWireRX 18 342 # define OMAP_INT_730_SMC_CD 19 343 # define OMAP_INT_730_SMC_IREQ 20 344 # define OMAP_INT_730_HDQ_1WIRE 21 345 # define OMAP_INT_730_TIMER32K 22 346 # define OMAP_INT_730_MMC_SDIO 23 347 # define OMAP_INT_730_UPLD 24 348 # define OMAP_INT_730_USB_HHC_1 27 349 # define OMAP_INT_730_USB_HHC_2 28 350 # define OMAP_INT_730_USB_GENI 29 351 # define OMAP_INT_730_USB_OTG 30 352 # define OMAP_INT_730_CAMERA_IF 31 353 # define OMAP_INT_730_RNG 32 354 # define OMAP_INT_730_DUAL_MODE_TIMER 33 355 # define OMAP_INT_730_DBB_RF_EN 34 356 # define OMAP_INT_730_MPUIO_KEYPAD 35 357 # define OMAP_INT_730_SHA1_MD5 36 358 # define OMAP_INT_730_SPI_100K_2 37 359 # define OMAP_INT_730_RNG_IDLE 38 360 # define OMAP_INT_730_MPUIO 39 361 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 362 # define OMAP_INT_730_LLPC_OE_FALLING 41 363 # define OMAP_INT_730_LLPC_OE_RISING 42 364 # define OMAP_INT_730_LLPC_VSYNC 43 365 # define OMAP_INT_730_WAKE_UP_REQ 46 366 # define OMAP_INT_730_DMA_CH6 53 367 # define OMAP_INT_730_DMA_CH7 54 368 # define OMAP_INT_730_DMA_CH8 55 369 # define OMAP_INT_730_DMA_CH9 56 370 # define OMAP_INT_730_DMA_CH10 57 371 # define OMAP_INT_730_DMA_CH11 58 372 # define OMAP_INT_730_DMA_CH12 59 373 # define OMAP_INT_730_DMA_CH13 60 374 # define OMAP_INT_730_DMA_CH14 61 375 # define OMAP_INT_730_DMA_CH15 62 376 # define OMAP_INT_730_NAND 63 377 378 /* 379 * OMAP-24xx common IRQ numbers 380 */ 381 # define OMAP_INT_24XX_STI 4 382 # define OMAP_INT_24XX_SYS_NIRQ 7 383 # define OMAP_INT_24XX_L3_IRQ 10 384 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 385 # define OMAP_INT_24XX_SDMA_IRQ0 12 386 # define OMAP_INT_24XX_SDMA_IRQ1 13 387 # define OMAP_INT_24XX_SDMA_IRQ2 14 388 # define OMAP_INT_24XX_SDMA_IRQ3 15 389 # define OMAP_INT_243X_MCBSP2_IRQ 16 390 # define OMAP_INT_243X_MCBSP3_IRQ 17 391 # define OMAP_INT_243X_MCBSP4_IRQ 18 392 # define OMAP_INT_243X_MCBSP5_IRQ 19 393 # define OMAP_INT_24XX_GPMC_IRQ 20 394 # define OMAP_INT_24XX_GUFFAW_IRQ 21 395 # define OMAP_INT_24XX_IVA_IRQ 22 396 # define OMAP_INT_24XX_EAC_IRQ 23 397 # define OMAP_INT_24XX_CAM_IRQ 24 398 # define OMAP_INT_24XX_DSS_IRQ 25 399 # define OMAP_INT_24XX_MAIL_U0_MPU 26 400 # define OMAP_INT_24XX_DSP_UMA 27 401 # define OMAP_INT_24XX_DSP_MMU 28 402 # define OMAP_INT_24XX_GPIO_BANK1 29 403 # define OMAP_INT_24XX_GPIO_BANK2 30 404 # define OMAP_INT_24XX_GPIO_BANK3 31 405 # define OMAP_INT_24XX_GPIO_BANK4 32 406 # define OMAP_INT_243X_GPIO_BANK5 33 407 # define OMAP_INT_24XX_MAIL_U3_MPU 34 408 # define OMAP_INT_24XX_WDT3 35 409 # define OMAP_INT_24XX_WDT4 36 410 # define OMAP_INT_24XX_GPTIMER1 37 411 # define OMAP_INT_24XX_GPTIMER2 38 412 # define OMAP_INT_24XX_GPTIMER3 39 413 # define OMAP_INT_24XX_GPTIMER4 40 414 # define OMAP_INT_24XX_GPTIMER5 41 415 # define OMAP_INT_24XX_GPTIMER6 42 416 # define OMAP_INT_24XX_GPTIMER7 43 417 # define OMAP_INT_24XX_GPTIMER8 44 418 # define OMAP_INT_24XX_GPTIMER9 45 419 # define OMAP_INT_24XX_GPTIMER10 46 420 # define OMAP_INT_24XX_GPTIMER11 47 421 # define OMAP_INT_24XX_GPTIMER12 48 422 # define OMAP_INT_24XX_PKA_IRQ 50 423 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 424 # define OMAP_INT_24XX_RNG_IRQ 52 425 # define OMAP_INT_24XX_MG_IRQ 53 426 # define OMAP_INT_24XX_I2C1_IRQ 56 427 # define OMAP_INT_24XX_I2C2_IRQ 57 428 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 429 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 430 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 431 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 432 # define OMAP_INT_243X_MCBSP1_IRQ 64 433 # define OMAP_INT_24XX_MCSPI1_IRQ 65 434 # define OMAP_INT_24XX_MCSPI2_IRQ 66 435 # define OMAP_INT_24XX_SSI1_IRQ0 67 436 # define OMAP_INT_24XX_SSI1_IRQ1 68 437 # define OMAP_INT_24XX_SSI2_IRQ0 69 438 # define OMAP_INT_24XX_SSI2_IRQ1 70 439 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 440 # define OMAP_INT_24XX_UART1_IRQ 72 441 # define OMAP_INT_24XX_UART2_IRQ 73 442 # define OMAP_INT_24XX_UART3_IRQ 74 443 # define OMAP_INT_24XX_USB_IRQ_GEN 75 444 # define OMAP_INT_24XX_USB_IRQ_NISO 76 445 # define OMAP_INT_24XX_USB_IRQ_ISO 77 446 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 447 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 448 # define OMAP_INT_24XX_USB_IRQ_OTG 80 449 # define OMAP_INT_24XX_VLYNQ_IRQ 81 450 # define OMAP_INT_24XX_MMC_IRQ 83 451 # define OMAP_INT_24XX_MS_IRQ 84 452 # define OMAP_INT_24XX_FAC_IRQ 85 453 # define OMAP_INT_24XX_MCSPI3_IRQ 91 454 # define OMAP_INT_243X_HS_USB_MC 92 455 # define OMAP_INT_243X_HS_USB_DMA 93 456 # define OMAP_INT_243X_CARKIT 94 457 # define OMAP_INT_34XX_GPTIMER12 95 458 459 /* omap_dma.c */ 460 enum omap_dma_model { 461 omap_dma_3_0, 462 omap_dma_3_1, 463 omap_dma_3_2, 464 omap_dma_4, 465 }; 466 467 struct soc_dma_s; 468 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 469 MemoryRegion *sysmem, 470 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 471 enum omap_dma_model model); 472 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 473 MemoryRegion *sysmem, 474 struct omap_mpu_state_s *mpu, int fifo, 475 int chans, omap_clk iclk, omap_clk fclk); 476 void omap_dma_reset(struct soc_dma_s *s); 477 478 struct dma_irq_map { 479 int ih; 480 int intr; 481 }; 482 483 /* Only used in OMAP DMA 3.x gigacells */ 484 enum omap_dma_port { 485 emiff = 0, 486 emifs, 487 imif, /* omap16xx: ocp_t1 */ 488 tipb, 489 local, /* omap16xx: ocp_t2 */ 490 tipb_mpui, 491 __omap_dma_port_last, 492 }; 493 494 typedef enum { 495 constant = 0, 496 post_incremented, 497 single_index, 498 double_index, 499 } omap_dma_addressing_t; 500 501 /* Only used in OMAP DMA 3.x gigacells */ 502 struct omap_dma_lcd_channel_s { 503 enum omap_dma_port src; 504 hwaddr src_f1_top; 505 hwaddr src_f1_bottom; 506 hwaddr src_f2_top; 507 hwaddr src_f2_bottom; 508 509 /* Used in OMAP DMA 3.2 gigacell */ 510 unsigned char brust_f1; 511 unsigned char pack_f1; 512 unsigned char data_type_f1; 513 unsigned char brust_f2; 514 unsigned char pack_f2; 515 unsigned char data_type_f2; 516 unsigned char end_prog; 517 unsigned char repeat; 518 unsigned char auto_init; 519 unsigned char priority; 520 unsigned char fs; 521 unsigned char running; 522 unsigned char bs; 523 unsigned char omap_3_1_compatible_disable; 524 unsigned char dst; 525 unsigned char lch_type; 526 int16_t element_index_f1; 527 int16_t element_index_f2; 528 int32_t frame_index_f1; 529 int32_t frame_index_f2; 530 uint16_t elements_f1; 531 uint16_t frames_f1; 532 uint16_t elements_f2; 533 uint16_t frames_f2; 534 omap_dma_addressing_t mode_f1; 535 omap_dma_addressing_t mode_f2; 536 537 /* Destination port is fixed. */ 538 int interrupts; 539 int condition; 540 int dual; 541 542 int current_frame; 543 hwaddr phys_framebuffer[2]; 544 qemu_irq irq; 545 struct omap_mpu_state_s *mpu; 546 } *omap_dma_get_lcdch(struct soc_dma_s *s); 547 548 /* 549 * DMA request numbers for OMAP1 550 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 551 */ 552 # define OMAP_DMA_NO_DEVICE 0 553 # define OMAP_DMA_MCSI1_TX 1 554 # define OMAP_DMA_MCSI1_RX 2 555 # define OMAP_DMA_I2C_RX 3 556 # define OMAP_DMA_I2C_TX 4 557 # define OMAP_DMA_EXT_NDMA_REQ0 5 558 # define OMAP_DMA_EXT_NDMA_REQ1 6 559 # define OMAP_DMA_UWIRE_TX 7 560 # define OMAP_DMA_MCBSP1_TX 8 561 # define OMAP_DMA_MCBSP1_RX 9 562 # define OMAP_DMA_MCBSP3_TX 10 563 # define OMAP_DMA_MCBSP3_RX 11 564 # define OMAP_DMA_UART1_TX 12 565 # define OMAP_DMA_UART1_RX 13 566 # define OMAP_DMA_UART2_TX 14 567 # define OMAP_DMA_UART2_RX 15 568 # define OMAP_DMA_MCBSP2_TX 16 569 # define OMAP_DMA_MCBSP2_RX 17 570 # define OMAP_DMA_UART3_TX 18 571 # define OMAP_DMA_UART3_RX 19 572 # define OMAP_DMA_CAMERA_IF_RX 20 573 # define OMAP_DMA_MMC_TX 21 574 # define OMAP_DMA_MMC_RX 22 575 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 576 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 577 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 578 # define OMAP_DMA_USB_W2FC_RX0 26 579 # define OMAP_DMA_USB_W2FC_RX1 27 580 # define OMAP_DMA_USB_W2FC_RX2 28 581 # define OMAP_DMA_USB_W2FC_TX0 29 582 # define OMAP_DMA_USB_W2FC_TX1 30 583 # define OMAP_DMA_USB_W2FC_TX2 31 584 585 /* These are only for 1610 */ 586 # define OMAP_DMA_CRYPTO_DES_IN 32 587 # define OMAP_DMA_SPI_TX 33 588 # define OMAP_DMA_SPI_RX 34 589 # define OMAP_DMA_CRYPTO_HASH 35 590 # define OMAP_DMA_CCP_ATTN 36 591 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 592 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 593 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 594 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 595 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 596 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 597 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 598 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 599 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 600 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 601 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 602 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 603 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 604 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 605 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 606 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 607 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 608 # define OMAP_DMA_MMC2_TX 54 609 # define OMAP_DMA_MMC2_RX 55 610 # define OMAP_DMA_CRYPTO_DES_OUT 56 611 612 /* 613 * DMA request numbers for the OMAP2 614 */ 615 # define OMAP24XX_DMA_NO_DEVICE 0 616 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 617 # define OMAP24XX_DMA_EXT_DMAREQ0 2 618 # define OMAP24XX_DMA_EXT_DMAREQ1 3 619 # define OMAP24XX_DMA_GPMC 4 620 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 621 # define OMAP24XX_DMA_DSS 6 622 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 623 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 624 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 625 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 626 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 627 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 628 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 629 # define OMAP24XX_DMA_EXT_DMAREQ2 14 630 # define OMAP24XX_DMA_EXT_DMAREQ3 15 631 # define OMAP24XX_DMA_EXT_DMAREQ4 16 632 # define OMAP24XX_DMA_EAC_AC_RD 17 633 # define OMAP24XX_DMA_EAC_AC_WR 18 634 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 635 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 636 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 637 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 638 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 639 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 640 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 641 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 642 # define OMAP24XX_DMA_I2C1_TX 27 643 # define OMAP24XX_DMA_I2C1_RX 28 644 # define OMAP24XX_DMA_I2C2_TX 29 645 # define OMAP24XX_DMA_I2C2_RX 30 646 # define OMAP24XX_DMA_MCBSP1_TX 31 647 # define OMAP24XX_DMA_MCBSP1_RX 32 648 # define OMAP24XX_DMA_MCBSP2_TX 33 649 # define OMAP24XX_DMA_MCBSP2_RX 34 650 # define OMAP24XX_DMA_SPI1_TX0 35 651 # define OMAP24XX_DMA_SPI1_RX0 36 652 # define OMAP24XX_DMA_SPI1_TX1 37 653 # define OMAP24XX_DMA_SPI1_RX1 38 654 # define OMAP24XX_DMA_SPI1_TX2 39 655 # define OMAP24XX_DMA_SPI1_RX2 40 656 # define OMAP24XX_DMA_SPI1_TX3 41 657 # define OMAP24XX_DMA_SPI1_RX3 42 658 # define OMAP24XX_DMA_SPI2_TX0 43 659 # define OMAP24XX_DMA_SPI2_RX0 44 660 # define OMAP24XX_DMA_SPI2_TX1 45 661 # define OMAP24XX_DMA_SPI2_RX1 46 662 663 # define OMAP24XX_DMA_UART1_TX 49 664 # define OMAP24XX_DMA_UART1_RX 50 665 # define OMAP24XX_DMA_UART2_TX 51 666 # define OMAP24XX_DMA_UART2_RX 52 667 # define OMAP24XX_DMA_UART3_TX 53 668 # define OMAP24XX_DMA_UART3_RX 54 669 # define OMAP24XX_DMA_USB_W2FC_TX0 55 670 # define OMAP24XX_DMA_USB_W2FC_RX0 56 671 # define OMAP24XX_DMA_USB_W2FC_TX1 57 672 # define OMAP24XX_DMA_USB_W2FC_RX1 58 673 # define OMAP24XX_DMA_USB_W2FC_TX2 59 674 # define OMAP24XX_DMA_USB_W2FC_RX2 60 675 # define OMAP24XX_DMA_MMC1_TX 61 676 # define OMAP24XX_DMA_MMC1_RX 62 677 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 678 # define OMAP24XX_DMA_EXT_DMAREQ5 64 679 680 /* omap[123].c */ 681 /* OMAP2 gp timer */ 682 struct omap_gp_timer_s; 683 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 684 qemu_irq irq, omap_clk fclk, omap_clk iclk); 685 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 686 687 /* OMAP2 sysctimer */ 688 struct omap_synctimer_s; 689 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 690 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 691 void omap_synctimer_reset(struct omap_synctimer_s *s); 692 693 struct omap_uart_s; 694 struct omap_uart_s *omap_uart_init(hwaddr base, 695 qemu_irq irq, omap_clk fclk, omap_clk iclk, 696 qemu_irq txdma, qemu_irq rxdma, 697 const char *label, Chardev *chr); 698 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 699 struct omap_target_agent_s *ta, 700 qemu_irq irq, omap_clk fclk, omap_clk iclk, 701 qemu_irq txdma, qemu_irq rxdma, 702 const char *label, Chardev *chr); 703 void omap_uart_reset(struct omap_uart_s *s); 704 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 705 706 struct omap_mpuio_s; 707 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 708 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 709 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 710 711 struct omap_uwire_s; 712 void omap_uwire_attach(struct omap_uwire_s *s, 713 uWireSlave *slave, int chipselect); 714 715 /* OMAP2 spi */ 716 struct omap_mcspi_s; 717 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 718 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 719 void omap_mcspi_attach(struct omap_mcspi_s *s, 720 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 721 int chipselect); 722 void omap_mcspi_reset(struct omap_mcspi_s *s); 723 724 struct I2SCodec { 725 void *opaque; 726 727 /* The CPU can call this if it is generating the clock signal on the 728 * i2s port. The CODEC can ignore it if it is set up as a clock 729 * master and generates its own clock. */ 730 void (*set_rate)(void *opaque, int in, int out); 731 732 void (*tx_swallow)(void *opaque); 733 qemu_irq rx_swallow; 734 qemu_irq tx_start; 735 736 int tx_rate; 737 int cts; 738 int rx_rate; 739 int rts; 740 741 struct i2s_fifo_s { 742 uint8_t *fifo; 743 int len; 744 int start; 745 int size; 746 } in, out; 747 }; 748 struct omap_mcbsp_s; 749 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 750 751 void omap_tap_init(struct omap_target_agent_s *ta, 752 struct omap_mpu_state_s *mpu); 753 754 /* omap_lcdc.c */ 755 struct omap_lcd_panel_s; 756 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 757 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 758 hwaddr base, 759 qemu_irq irq, 760 struct omap_dma_lcd_channel_s *dma, 761 omap_clk clk); 762 763 /* omap_dss.c */ 764 struct rfbi_chip_s { 765 void *opaque; 766 void (*write)(void *opaque, int dc, uint16_t value); 767 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 768 uint16_t (*read)(void *opaque, int dc); 769 }; 770 struct omap_dss_s; 771 void omap_dss_reset(struct omap_dss_s *s); 772 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 773 MemoryRegion *sysmem, 774 hwaddr l3_base, 775 qemu_irq irq, qemu_irq drq, 776 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 777 omap_clk ick1, omap_clk ick2); 778 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 779 780 /* omap_mmc.c */ 781 struct omap_mmc_s; 782 struct omap_mmc_s *omap_mmc_init(hwaddr base, 783 MemoryRegion *sysmem, 784 BlockBackend *blk, 785 qemu_irq irq, qemu_irq dma[], omap_clk clk); 786 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 787 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 788 omap_clk fclk, omap_clk iclk); 789 void omap_mmc_reset(struct omap_mmc_s *s); 790 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 791 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 792 793 /* omap_i2c.c */ 794 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 795 796 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 797 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 798 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 799 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 800 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 801 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 802 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 803 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 804 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 805 806 # define cpu_is_omap15xx(cpu) \ 807 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 808 # define cpu_is_omap16xx(cpu) \ 809 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 810 # define cpu_is_omap24xx(cpu) \ 811 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 812 813 # define cpu_class_omap1(cpu) \ 814 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 815 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 816 # define cpu_class_omap3(cpu) \ 817 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 818 819 struct omap_mpu_state_s { 820 enum omap_mpu_model { 821 omap310, 822 omap1510, 823 omap1610, 824 omap1710, 825 omap2410, 826 omap2420, 827 omap2422, 828 omap2423, 829 omap2430, 830 omap3430, 831 omap3630, 832 } mpu_model; 833 834 ARMCPU *cpu; 835 836 qemu_irq *drq; 837 838 qemu_irq wakeup; 839 840 MemoryRegion ulpd_pm_iomem; 841 MemoryRegion pin_cfg_iomem; 842 MemoryRegion id_iomem; 843 MemoryRegion id_iomem_e18; 844 MemoryRegion id_iomem_ed4; 845 MemoryRegion id_iomem_e20; 846 MemoryRegion mpui_iomem; 847 MemoryRegion tcmi_iomem; 848 MemoryRegion clkm_iomem; 849 MemoryRegion clkdsp_iomem; 850 MemoryRegion mpui_io_iomem; 851 MemoryRegion tap_iomem; 852 MemoryRegion imif_ram; 853 MemoryRegion sram; 854 855 struct omap_dma_port_if_s { 856 uint32_t (*read[3])(struct omap_mpu_state_s *s, 857 hwaddr offset); 858 void (*write[3])(struct omap_mpu_state_s *s, 859 hwaddr offset, uint32_t value); 860 int (*addr_valid)(struct omap_mpu_state_s *s, 861 hwaddr addr); 862 } port[__omap_dma_port_last]; 863 864 uint64_t sdram_size; 865 unsigned long sram_size; 866 867 /* MPUI-TIPB peripherals */ 868 struct omap_uart_s *uart[3]; 869 870 DeviceState *gpio; 871 872 struct omap_mcbsp_s *mcbsp1; 873 struct omap_mcbsp_s *mcbsp3; 874 875 /* MPU public TIPB peripherals */ 876 struct omap_32khz_timer_s *os_timer; 877 878 struct omap_mmc_s *mmc; 879 880 struct omap_mpuio_s *mpuio; 881 882 struct omap_uwire_s *microwire; 883 884 struct omap_pwl_s *pwl; 885 struct omap_pwt_s *pwt; 886 DeviceState *i2c[2]; 887 888 struct omap_rtc_s *rtc; 889 890 struct omap_mcbsp_s *mcbsp2; 891 892 struct omap_lpg_s *led[2]; 893 894 /* MPU private TIPB peripherals */ 895 DeviceState *ih[2]; 896 897 struct soc_dma_s *dma; 898 899 struct omap_mpu_timer_s *timer[3]; 900 struct omap_watchdog_timer_s *wdt; 901 902 struct omap_lcd_panel_s *lcd; 903 904 uint32_t ulpd_pm_regs[21]; 905 int64_t ulpd_gauge_start; 906 907 uint32_t func_mux_ctrl[14]; 908 uint32_t comp_mode_ctrl[1]; 909 uint32_t pull_dwn_ctrl[4]; 910 uint32_t gate_inh_ctrl[1]; 911 uint32_t voltage_ctrl[1]; 912 uint32_t test_dbg_ctrl[1]; 913 uint32_t mod_conf_ctrl[1]; 914 int compat1509; 915 916 uint32_t mpui_ctrl; 917 918 struct omap_tipb_bridge_s *private_tipb; 919 struct omap_tipb_bridge_s *public_tipb; 920 921 uint32_t tcmi_regs[17]; 922 923 struct dpll_ctl_s *dpll[3]; 924 925 omap_clk clks; 926 struct { 927 int cold_start; 928 int clocking_scheme; 929 uint16_t arm_ckctl; 930 uint16_t arm_idlect1; 931 uint16_t arm_idlect2; 932 uint16_t arm_ewupct; 933 uint16_t arm_rstct1; 934 uint16_t arm_rstct2; 935 uint16_t arm_ckout1; 936 int dpll1_mode; 937 uint16_t dsp_idlect1; 938 uint16_t dsp_idlect2; 939 uint16_t dsp_rstct2; 940 } clkm; 941 942 /* OMAP2-only peripherals */ 943 struct omap_l4_s *l4; 944 945 struct omap_gp_timer_s *gptimer[12]; 946 struct omap_synctimer_s *synctimer; 947 948 struct omap_prcm_s *prcm; 949 struct omap_sdrc_s *sdrc; 950 struct omap_gpmc_s *gpmc; 951 struct omap_sysctl_s *sysc; 952 953 struct omap_mcspi_s *mcspi[2]; 954 955 struct omap_dss_s *dss; 956 957 struct omap_eac_s *eac; 958 }; 959 960 /* omap1.c */ 961 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 962 const char *core); 963 964 /* omap2.c */ 965 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 966 const char *core); 967 968 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 969 void omap_badwidth_write8(void *opaque, hwaddr addr, 970 uint32_t value); 971 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 972 void omap_badwidth_write16(void *opaque, hwaddr addr, 973 uint32_t value); 974 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 975 void omap_badwidth_write32(void *opaque, hwaddr addr, 976 uint32_t value); 977 978 void omap_mpu_wakeup(void *opaque, int irq, int req); 979 980 # define OMAP_BAD_REG(paddr) \ 981 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 982 __func__, paddr) 983 # define OMAP_RO_REG(paddr) \ 984 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 985 HWADDR_PRIx "\n", \ 986 __func__, paddr) 987 988 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 989 (Board-specifc tags are not here) */ 990 #define OMAP_TAG_CLOCK 0x4f01 991 #define OMAP_TAG_MMC 0x4f02 992 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 993 #define OMAP_TAG_USB 0x4f04 994 #define OMAP_TAG_LCD 0x4f05 995 #define OMAP_TAG_GPIO_SWITCH 0x4f06 996 #define OMAP_TAG_UART 0x4f07 997 #define OMAP_TAG_FBMEM 0x4f08 998 #define OMAP_TAG_STI_CONSOLE 0x4f09 999 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1000 #define OMAP_TAG_PARTITION 0x4f0b 1001 #define OMAP_TAG_TEA5761 0x4f10 1002 #define OMAP_TAG_TMP105 0x4f11 1003 #define OMAP_TAG_BOOT_REASON 0x4f80 1004 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1005 #define OMAP_TAG_VERSION_STR 0x4f82 1006 1007 enum { 1008 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1009 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1010 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1011 }; 1012 1013 #define OMAP_GPIOSW_INVERTED 0x0001 1014 #define OMAP_GPIOSW_OUTPUT 0x0002 1015 1016 # define OMAP_MPUI_REG_MASK 0x000007ff 1017 1018 #endif 1019