10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * Texas Instruments OMAP processors. 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 50d09e41aSPaolo Bonzini * 60d09e41aSPaolo Bonzini * This program is free software; you can redistribute it and/or 70d09e41aSPaolo Bonzini * modify it under the terms of the GNU General Public License as 80d09e41aSPaolo Bonzini * published by the Free Software Foundation; either version 2 or 90d09e41aSPaolo Bonzini * (at your option) version 3 of the License. 100d09e41aSPaolo Bonzini * 110d09e41aSPaolo Bonzini * This program is distributed in the hope that it will be useful, 120d09e41aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 130d09e41aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140d09e41aSPaolo Bonzini * GNU General Public License for more details. 150d09e41aSPaolo Bonzini * 160d09e41aSPaolo Bonzini * You should have received a copy of the GNU General Public License along 170d09e41aSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 180d09e41aSPaolo Bonzini */ 190d09e41aSPaolo Bonzini #ifndef hw_omap_h 200d09e41aSPaolo Bonzini #include "exec/memory.h" 210d09e41aSPaolo Bonzini # define hw_omap_h "omap.h" 220d09e41aSPaolo Bonzini #include "hw/irq.h" 23*a331dd02SPhilippe Mathieu-Daudé #include "hw/input/tsc2xxx.h" 24fcf5ef2aSThomas Huth #include "target/arm/cpu-qom.h" 2584b335c6SPhilippe Mathieu-Daudé #include "qemu/log.h" 260d09e41aSPaolo Bonzini 270d09e41aSPaolo Bonzini # define OMAP_EMIFS_BASE 0x00000000 280d09e41aSPaolo Bonzini # define OMAP2_Q0_BASE 0x00000000 290d09e41aSPaolo Bonzini # define OMAP_CS0_BASE 0x00000000 300d09e41aSPaolo Bonzini # define OMAP_CS1_BASE 0x04000000 310d09e41aSPaolo Bonzini # define OMAP_CS2_BASE 0x08000000 320d09e41aSPaolo Bonzini # define OMAP_CS3_BASE 0x0c000000 330d09e41aSPaolo Bonzini # define OMAP_EMIFF_BASE 0x10000000 340d09e41aSPaolo Bonzini # define OMAP_IMIF_BASE 0x20000000 350d09e41aSPaolo Bonzini # define OMAP_LOCALBUS_BASE 0x30000000 360d09e41aSPaolo Bonzini # define OMAP2_Q1_BASE 0x40000000 370d09e41aSPaolo Bonzini # define OMAP2_L4_BASE 0x48000000 380d09e41aSPaolo Bonzini # define OMAP2_SRAM_BASE 0x40200000 390d09e41aSPaolo Bonzini # define OMAP2_L3_BASE 0x68000000 400d09e41aSPaolo Bonzini # define OMAP2_Q2_BASE 0x80000000 410d09e41aSPaolo Bonzini # define OMAP2_Q3_BASE 0xc0000000 420d09e41aSPaolo Bonzini # define OMAP_MPUI_BASE 0xe1000000 430d09e41aSPaolo Bonzini 440d09e41aSPaolo Bonzini # define OMAP730_SRAM_SIZE 0x00032000 450d09e41aSPaolo Bonzini # define OMAP15XX_SRAM_SIZE 0x00030000 460d09e41aSPaolo Bonzini # define OMAP16XX_SRAM_SIZE 0x00004000 470d09e41aSPaolo Bonzini # define OMAP1611_SRAM_SIZE 0x0003e800 480d09e41aSPaolo Bonzini # define OMAP242X_SRAM_SIZE 0x000a0000 490d09e41aSPaolo Bonzini # define OMAP243X_SRAM_SIZE 0x00010000 500d09e41aSPaolo Bonzini # define OMAP_CS0_SIZE 0x04000000 510d09e41aSPaolo Bonzini # define OMAP_CS1_SIZE 0x04000000 520d09e41aSPaolo Bonzini # define OMAP_CS2_SIZE 0x04000000 530d09e41aSPaolo Bonzini # define OMAP_CS3_SIZE 0x04000000 540d09e41aSPaolo Bonzini 550d09e41aSPaolo Bonzini /* omap_clk.c */ 560d09e41aSPaolo Bonzini struct omap_mpu_state_s; 570d09e41aSPaolo Bonzini typedef struct clk *omap_clk; 580d09e41aSPaolo Bonzini omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 590d09e41aSPaolo Bonzini void omap_clk_init(struct omap_mpu_state_s *mpu); 600d09e41aSPaolo Bonzini void omap_clk_adduser(struct clk *clk, qemu_irq user); 610d09e41aSPaolo Bonzini void omap_clk_get(omap_clk clk); 620d09e41aSPaolo Bonzini void omap_clk_put(omap_clk clk); 630d09e41aSPaolo Bonzini void omap_clk_onoff(omap_clk clk, int on); 640d09e41aSPaolo Bonzini void omap_clk_canidle(omap_clk clk, int can); 650d09e41aSPaolo Bonzini void omap_clk_setrate(omap_clk clk, int divide, int multiply); 660d09e41aSPaolo Bonzini int64_t omap_clk_getrate(omap_clk clk); 670d09e41aSPaolo Bonzini void omap_clk_reparent(omap_clk clk, omap_clk parent); 680d09e41aSPaolo Bonzini 690d09e41aSPaolo Bonzini /* OMAP2 l4 Interconnect */ 700d09e41aSPaolo Bonzini struct omap_l4_s; 710d09e41aSPaolo Bonzini struct omap_l4_region_s { 720d09e41aSPaolo Bonzini hwaddr offset; 730d09e41aSPaolo Bonzini size_t size; 740d09e41aSPaolo Bonzini int access; 750d09e41aSPaolo Bonzini }; 760d09e41aSPaolo Bonzini struct omap_l4_agent_info_s { 770d09e41aSPaolo Bonzini int ta; 780d09e41aSPaolo Bonzini int region; 790d09e41aSPaolo Bonzini int regions; 800d09e41aSPaolo Bonzini int ta_region; 810d09e41aSPaolo Bonzini }; 820d09e41aSPaolo Bonzini struct omap_target_agent_s { 830d09e41aSPaolo Bonzini MemoryRegion iomem; 840d09e41aSPaolo Bonzini struct omap_l4_s *bus; 850d09e41aSPaolo Bonzini int regions; 860d09e41aSPaolo Bonzini const struct omap_l4_region_s *start; 870d09e41aSPaolo Bonzini hwaddr base; 880d09e41aSPaolo Bonzini uint32_t component; 890d09e41aSPaolo Bonzini uint32_t control; 900d09e41aSPaolo Bonzini uint32_t status; 910d09e41aSPaolo Bonzini }; 920d09e41aSPaolo Bonzini struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 930d09e41aSPaolo Bonzini hwaddr base, int ta_num); 940d09e41aSPaolo Bonzini 950d09e41aSPaolo Bonzini struct omap_target_agent_s; 960d09e41aSPaolo Bonzini struct omap_target_agent_s *omap_l4ta_get( 970d09e41aSPaolo Bonzini struct omap_l4_s *bus, 980d09e41aSPaolo Bonzini const struct omap_l4_region_s *regions, 990d09e41aSPaolo Bonzini const struct omap_l4_agent_info_s *agents, 1000d09e41aSPaolo Bonzini int cs); 1010d09e41aSPaolo Bonzini hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 1020d09e41aSPaolo Bonzini int region, MemoryRegion *mr); 1030d09e41aSPaolo Bonzini hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 1040d09e41aSPaolo Bonzini int region); 1050d09e41aSPaolo Bonzini hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 1060d09e41aSPaolo Bonzini int region); 1070d09e41aSPaolo Bonzini 1080d09e41aSPaolo Bonzini /* OMAP2 SDRAM controller */ 1090d09e41aSPaolo Bonzini struct omap_sdrc_s; 1100d09e41aSPaolo Bonzini struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 1110d09e41aSPaolo Bonzini hwaddr base); 1120d09e41aSPaolo Bonzini void omap_sdrc_reset(struct omap_sdrc_s *s); 1130d09e41aSPaolo Bonzini 1140d09e41aSPaolo Bonzini /* OMAP2 general purpose memory controller */ 1150d09e41aSPaolo Bonzini struct omap_gpmc_s; 1160d09e41aSPaolo Bonzini struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 1170d09e41aSPaolo Bonzini hwaddr base, 1180d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq drq); 1190d09e41aSPaolo Bonzini void omap_gpmc_reset(struct omap_gpmc_s *s); 1200d09e41aSPaolo Bonzini void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 1210d09e41aSPaolo Bonzini void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 1220d09e41aSPaolo Bonzini 1230d09e41aSPaolo Bonzini /* 1240d09e41aSPaolo Bonzini * Common IRQ numbers for level 1 interrupt handler 1250d09e41aSPaolo Bonzini * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 1260d09e41aSPaolo Bonzini */ 1270d09e41aSPaolo Bonzini # define OMAP_INT_CAMERA 1 1280d09e41aSPaolo Bonzini # define OMAP_INT_FIQ 3 1290d09e41aSPaolo Bonzini # define OMAP_INT_RTDX 6 1300d09e41aSPaolo Bonzini # define OMAP_INT_DSP_MMU_ABORT 7 1310d09e41aSPaolo Bonzini # define OMAP_INT_HOST 8 1320d09e41aSPaolo Bonzini # define OMAP_INT_ABORT 9 1330d09e41aSPaolo Bonzini # define OMAP_INT_BRIDGE_PRIV 13 1340d09e41aSPaolo Bonzini # define OMAP_INT_GPIO_BANK1 14 1350d09e41aSPaolo Bonzini # define OMAP_INT_UART3 15 1360d09e41aSPaolo Bonzini # define OMAP_INT_TIMER3 16 1370d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH0_6 19 1380d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH1_7 20 1390d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH2_8 21 1400d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH3 22 1410d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH4 23 1420d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH5 24 1430d09e41aSPaolo Bonzini # define OMAP_INT_DMA_LCD 25 1440d09e41aSPaolo Bonzini # define OMAP_INT_TIMER1 26 1450d09e41aSPaolo Bonzini # define OMAP_INT_WD_TIMER 27 1460d09e41aSPaolo Bonzini # define OMAP_INT_BRIDGE_PUB 28 1470d09e41aSPaolo Bonzini # define OMAP_INT_TIMER2 30 1480d09e41aSPaolo Bonzini # define OMAP_INT_LCD_CTRL 31 1490d09e41aSPaolo Bonzini 1500d09e41aSPaolo Bonzini /* 1510d09e41aSPaolo Bonzini * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 1520d09e41aSPaolo Bonzini */ 1530d09e41aSPaolo Bonzini # define OMAP_INT_15XX_IH2_IRQ 0 1540d09e41aSPaolo Bonzini # define OMAP_INT_15XX_LB_MMU 17 1550d09e41aSPaolo Bonzini # define OMAP_INT_15XX_LOCAL_BUS 29 1560d09e41aSPaolo Bonzini 1570d09e41aSPaolo Bonzini /* 1580d09e41aSPaolo Bonzini * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 1590d09e41aSPaolo Bonzini */ 1600d09e41aSPaolo Bonzini # define OMAP_INT_1510_SPI_TX 4 1610d09e41aSPaolo Bonzini # define OMAP_INT_1510_SPI_RX 5 1620d09e41aSPaolo Bonzini # define OMAP_INT_1510_DSP_MAILBOX1 10 1630d09e41aSPaolo Bonzini # define OMAP_INT_1510_DSP_MAILBOX2 11 1640d09e41aSPaolo Bonzini 1650d09e41aSPaolo Bonzini /* 1660d09e41aSPaolo Bonzini * OMAP-310 specific IRQ numbers for level 1 interrupt handler 1670d09e41aSPaolo Bonzini */ 1680d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2_TX 4 1690d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2_RX 5 1700d09e41aSPaolo Bonzini # define OMAP_INT_310_HSB_MAILBOX1 12 1710d09e41aSPaolo Bonzini # define OMAP_INT_310_HSAB_MMU 18 1720d09e41aSPaolo Bonzini 1730d09e41aSPaolo Bonzini /* 1740d09e41aSPaolo Bonzini * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 1750d09e41aSPaolo Bonzini */ 1760d09e41aSPaolo Bonzini # define OMAP_INT_1610_IH2_IRQ 0 1770d09e41aSPaolo Bonzini # define OMAP_INT_1610_IH2_FIQ 2 1780d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2_TX 4 1790d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2_RX 5 1800d09e41aSPaolo Bonzini # define OMAP_INT_1610_DSP_MAILBOX1 10 1810d09e41aSPaolo Bonzini # define OMAP_INT_1610_DSP_MAILBOX2 11 1820d09e41aSPaolo Bonzini # define OMAP_INT_1610_LCD_LINE 12 1830d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER1 17 1840d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER2 18 1850d09e41aSPaolo Bonzini # define OMAP_INT_1610_SSR_FIFO_0 29 1860d09e41aSPaolo Bonzini 1870d09e41aSPaolo Bonzini /* 1880d09e41aSPaolo Bonzini * OMAP-730 specific IRQ numbers for level 1 interrupt handler 1890d09e41aSPaolo Bonzini */ 1900d09e41aSPaolo Bonzini # define OMAP_INT_730_IH2_FIQ 0 1910d09e41aSPaolo Bonzini # define OMAP_INT_730_IH2_IRQ 1 1920d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_NON_ISO 2 1930d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_ISO 3 1940d09e41aSPaolo Bonzini # define OMAP_INT_730_ICR 4 1950d09e41aSPaolo Bonzini # define OMAP_INT_730_EAC 5 1960d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK1 6 1970d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK2 7 1980d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK3 8 1990d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2TX 10 2000d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2RX 11 2010d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2RX_OVF 12 2020d09e41aSPaolo Bonzini # define OMAP_INT_730_LCD_LINE 14 2030d09e41aSPaolo Bonzini # define OMAP_INT_730_GSM_PROTECT 15 2040d09e41aSPaolo Bonzini # define OMAP_INT_730_TIMER3 16 2050d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK5 17 2060d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK6 18 2070d09e41aSPaolo Bonzini # define OMAP_INT_730_SPGIO_WR 29 2080d09e41aSPaolo Bonzini 2090d09e41aSPaolo Bonzini /* 2100d09e41aSPaolo Bonzini * Common IRQ numbers for level 2 interrupt handler 2110d09e41aSPaolo Bonzini */ 2120d09e41aSPaolo Bonzini # define OMAP_INT_KEYBOARD 1 2130d09e41aSPaolo Bonzini # define OMAP_INT_uWireTX 2 2140d09e41aSPaolo Bonzini # define OMAP_INT_uWireRX 3 2150d09e41aSPaolo Bonzini # define OMAP_INT_I2C 4 2160d09e41aSPaolo Bonzini # define OMAP_INT_MPUIO 5 2170d09e41aSPaolo Bonzini # define OMAP_INT_USB_HHC_1 6 2180d09e41aSPaolo Bonzini # define OMAP_INT_McBSP3TX 10 2190d09e41aSPaolo Bonzini # define OMAP_INT_McBSP3RX 11 2200d09e41aSPaolo Bonzini # define OMAP_INT_McBSP1TX 12 2210d09e41aSPaolo Bonzini # define OMAP_INT_McBSP1RX 13 2220d09e41aSPaolo Bonzini # define OMAP_INT_UART1 14 2230d09e41aSPaolo Bonzini # define OMAP_INT_UART2 15 2240d09e41aSPaolo Bonzini # define OMAP_INT_USB_W2FC 20 2250d09e41aSPaolo Bonzini # define OMAP_INT_1WIRE 21 2260d09e41aSPaolo Bonzini # define OMAP_INT_OS_TIMER 22 2270d09e41aSPaolo Bonzini # define OMAP_INT_OQN 23 2280d09e41aSPaolo Bonzini # define OMAP_INT_GAUGE_32K 24 2290d09e41aSPaolo Bonzini # define OMAP_INT_RTC_TIMER 25 2300d09e41aSPaolo Bonzini # define OMAP_INT_RTC_ALARM 26 2310d09e41aSPaolo Bonzini # define OMAP_INT_DSP_MMU 28 2320d09e41aSPaolo Bonzini 2330d09e41aSPaolo Bonzini /* 2340d09e41aSPaolo Bonzini * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 2350d09e41aSPaolo Bonzini */ 2360d09e41aSPaolo Bonzini # define OMAP_INT_1510_BT_MCSI1TX 16 2370d09e41aSPaolo Bonzini # define OMAP_INT_1510_BT_MCSI1RX 17 2380d09e41aSPaolo Bonzini # define OMAP_INT_1510_SoSSI_MATCH 19 2390d09e41aSPaolo Bonzini # define OMAP_INT_1510_MEM_STICK 27 2400d09e41aSPaolo Bonzini # define OMAP_INT_1510_COM_SPI_RO 31 2410d09e41aSPaolo Bonzini 2420d09e41aSPaolo Bonzini /* 2430d09e41aSPaolo Bonzini * OMAP-310 specific IRQ numbers for level 2 interrupt handler 2440d09e41aSPaolo Bonzini */ 2450d09e41aSPaolo Bonzini # define OMAP_INT_310_FAC 0 2460d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_HHC_2 7 2470d09e41aSPaolo Bonzini # define OMAP_INT_310_MCSI1_FE 16 2480d09e41aSPaolo Bonzini # define OMAP_INT_310_MCSI2_FE 17 2490d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_W2FC_ISO 29 2500d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_W2FC_NON_ISO 30 2510d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2RX_OF 31 2520d09e41aSPaolo Bonzini 2530d09e41aSPaolo Bonzini /* 2540d09e41aSPaolo Bonzini * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 2550d09e41aSPaolo Bonzini */ 2560d09e41aSPaolo Bonzini # define OMAP_INT_1610_FAC 0 2570d09e41aSPaolo Bonzini # define OMAP_INT_1610_USB_HHC_2 7 2580d09e41aSPaolo Bonzini # define OMAP_INT_1610_USB_OTG 8 2590d09e41aSPaolo Bonzini # define OMAP_INT_1610_SoSSI 9 2600d09e41aSPaolo Bonzini # define OMAP_INT_1610_BT_MCSI1TX 16 2610d09e41aSPaolo Bonzini # define OMAP_INT_1610_BT_MCSI1RX 17 2620d09e41aSPaolo Bonzini # define OMAP_INT_1610_SoSSI_MATCH 19 2630d09e41aSPaolo Bonzini # define OMAP_INT_1610_MEM_STICK 27 2640d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2RX_OF 31 2650d09e41aSPaolo Bonzini # define OMAP_INT_1610_STI 32 2660d09e41aSPaolo Bonzini # define OMAP_INT_1610_STI_WAKEUP 33 2670d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER3 34 2680d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER4 35 2690d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER5 36 2700d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER6 37 2710d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER7 38 2720d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER8 39 2730d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK2 40 2740d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK3 41 2750d09e41aSPaolo Bonzini # define OMAP_INT_1610_MMC2 42 2760d09e41aSPaolo Bonzini # define OMAP_INT_1610_CF 43 2770d09e41aSPaolo Bonzini # define OMAP_INT_1610_WAKE_UP_REQ 46 2780d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK4 48 2790d09e41aSPaolo Bonzini # define OMAP_INT_1610_SPI 49 2800d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH6 53 2810d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH7 54 2820d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH8 55 2830d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH9 56 2840d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH10 57 2850d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH11 58 2860d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH12 59 2870d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH13 60 2880d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH14 61 2890d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH15 62 2900d09e41aSPaolo Bonzini # define OMAP_INT_1610_NAND 63 2910d09e41aSPaolo Bonzini 2920d09e41aSPaolo Bonzini /* 2930d09e41aSPaolo Bonzini * OMAP-730 specific IRQ numbers for level 2 interrupt handler 2940d09e41aSPaolo Bonzini */ 2950d09e41aSPaolo Bonzini # define OMAP_INT_730_HW_ERRORS 0 2960d09e41aSPaolo Bonzini # define OMAP_INT_730_NFIQ_PWR_FAIL 1 2970d09e41aSPaolo Bonzini # define OMAP_INT_730_CFCD 2 2980d09e41aSPaolo Bonzini # define OMAP_INT_730_CFIREQ 3 2990d09e41aSPaolo Bonzini # define OMAP_INT_730_I2C 4 3000d09e41aSPaolo Bonzini # define OMAP_INT_730_PCC 5 3010d09e41aSPaolo Bonzini # define OMAP_INT_730_MPU_EXT_NIRQ 6 3020d09e41aSPaolo Bonzini # define OMAP_INT_730_SPI_100K_1 7 3030d09e41aSPaolo Bonzini # define OMAP_INT_730_SYREN_SPI 8 3040d09e41aSPaolo Bonzini # define OMAP_INT_730_VLYNQ 9 3050d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK4 10 3060d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1TX 11 3070d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1RX 12 3080d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1RX_OF 13 3090d09e41aSPaolo Bonzini # define OMAP_INT_730_UART_MODEM_IRDA_2 14 3100d09e41aSPaolo Bonzini # define OMAP_INT_730_UART_MODEM_1 15 3110d09e41aSPaolo Bonzini # define OMAP_INT_730_MCSI 16 3120d09e41aSPaolo Bonzini # define OMAP_INT_730_uWireTX 17 3130d09e41aSPaolo Bonzini # define OMAP_INT_730_uWireRX 18 3140d09e41aSPaolo Bonzini # define OMAP_INT_730_SMC_CD 19 3150d09e41aSPaolo Bonzini # define OMAP_INT_730_SMC_IREQ 20 3160d09e41aSPaolo Bonzini # define OMAP_INT_730_HDQ_1WIRE 21 3170d09e41aSPaolo Bonzini # define OMAP_INT_730_TIMER32K 22 3180d09e41aSPaolo Bonzini # define OMAP_INT_730_MMC_SDIO 23 3190d09e41aSPaolo Bonzini # define OMAP_INT_730_UPLD 24 3200d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_HHC_1 27 3210d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_HHC_2 28 3220d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_GENI 29 3230d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_OTG 30 3240d09e41aSPaolo Bonzini # define OMAP_INT_730_CAMERA_IF 31 3250d09e41aSPaolo Bonzini # define OMAP_INT_730_RNG 32 3260d09e41aSPaolo Bonzini # define OMAP_INT_730_DUAL_MODE_TIMER 33 3270d09e41aSPaolo Bonzini # define OMAP_INT_730_DBB_RF_EN 34 3280d09e41aSPaolo Bonzini # define OMAP_INT_730_MPUIO_KEYPAD 35 3290d09e41aSPaolo Bonzini # define OMAP_INT_730_SHA1_MD5 36 3300d09e41aSPaolo Bonzini # define OMAP_INT_730_SPI_100K_2 37 3310d09e41aSPaolo Bonzini # define OMAP_INT_730_RNG_IDLE 38 3320d09e41aSPaolo Bonzini # define OMAP_INT_730_MPUIO 39 3330d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 3340d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_OE_FALLING 41 3350d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_OE_RISING 42 3360d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_VSYNC 43 3370d09e41aSPaolo Bonzini # define OMAP_INT_730_WAKE_UP_REQ 46 3380d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH6 53 3390d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH7 54 3400d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH8 55 3410d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH9 56 3420d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH10 57 3430d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH11 58 3440d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH12 59 3450d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH13 60 3460d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH14 61 3470d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH15 62 3480d09e41aSPaolo Bonzini # define OMAP_INT_730_NAND 63 3490d09e41aSPaolo Bonzini 3500d09e41aSPaolo Bonzini /* 3510d09e41aSPaolo Bonzini * OMAP-24xx common IRQ numbers 3520d09e41aSPaolo Bonzini */ 3530d09e41aSPaolo Bonzini # define OMAP_INT_24XX_STI 4 3540d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SYS_NIRQ 7 3550d09e41aSPaolo Bonzini # define OMAP_INT_24XX_L3_IRQ 10 3560d09e41aSPaolo Bonzini # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 3570d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ0 12 3580d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ1 13 3590d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ2 14 3600d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ3 15 3610d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP2_IRQ 16 3620d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP3_IRQ 17 3630d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP4_IRQ 18 3640d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP5_IRQ 19 3650d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPMC_IRQ 20 3660d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GUFFAW_IRQ 21 3670d09e41aSPaolo Bonzini # define OMAP_INT_24XX_IVA_IRQ 22 3680d09e41aSPaolo Bonzini # define OMAP_INT_24XX_EAC_IRQ 23 3690d09e41aSPaolo Bonzini # define OMAP_INT_24XX_CAM_IRQ 24 3700d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSS_IRQ 25 3710d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MAIL_U0_MPU 26 3720d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSP_UMA 27 3730d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSP_MMU 28 3740d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK1 29 3750d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK2 30 3760d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK3 31 3770d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK4 32 3780d09e41aSPaolo Bonzini # define OMAP_INT_243X_GPIO_BANK5 33 3790d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MAIL_U3_MPU 34 3800d09e41aSPaolo Bonzini # define OMAP_INT_24XX_WDT3 35 3810d09e41aSPaolo Bonzini # define OMAP_INT_24XX_WDT4 36 3820d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER1 37 3830d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER2 38 3840d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER3 39 3850d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER4 40 3860d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER5 41 3870d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER6 42 3880d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER7 43 3890d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER8 44 3900d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER9 45 3910d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER10 46 3920d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER11 47 3930d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER12 48 3940d09e41aSPaolo Bonzini # define OMAP_INT_24XX_PKA_IRQ 50 3950d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SHA1MD5_IRQ 51 3960d09e41aSPaolo Bonzini # define OMAP_INT_24XX_RNG_IRQ 52 3970d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MG_IRQ 53 3980d09e41aSPaolo Bonzini # define OMAP_INT_24XX_I2C1_IRQ 56 3990d09e41aSPaolo Bonzini # define OMAP_INT_24XX_I2C2_IRQ 57 4000d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 4010d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 4020d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 4030d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 4040d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP1_IRQ 64 4050d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI1_IRQ 65 4060d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI2_IRQ 66 4070d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI1_IRQ0 67 4080d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI1_IRQ1 68 4090d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI2_IRQ0 69 4100d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI2_IRQ1 70 4110d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI_GDD_IRQ 71 4120d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART1_IRQ 72 4130d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART2_IRQ 73 4140d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART3_IRQ 74 4150d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_GEN 75 4160d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_NISO 76 4170d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_ISO 77 4180d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_HGEN 78 4190d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_HSOF 79 4200d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_OTG 80 4210d09e41aSPaolo Bonzini # define OMAP_INT_24XX_VLYNQ_IRQ 81 4220d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MMC_IRQ 83 4230d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MS_IRQ 84 4240d09e41aSPaolo Bonzini # define OMAP_INT_24XX_FAC_IRQ 85 4250d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI3_IRQ 91 4260d09e41aSPaolo Bonzini # define OMAP_INT_243X_HS_USB_MC 92 4270d09e41aSPaolo Bonzini # define OMAP_INT_243X_HS_USB_DMA 93 4280d09e41aSPaolo Bonzini # define OMAP_INT_243X_CARKIT 94 4290d09e41aSPaolo Bonzini # define OMAP_INT_34XX_GPTIMER12 95 4300d09e41aSPaolo Bonzini 4310d09e41aSPaolo Bonzini /* omap_dma.c */ 4320d09e41aSPaolo Bonzini enum omap_dma_model { 4330d09e41aSPaolo Bonzini omap_dma_3_0, 4340d09e41aSPaolo Bonzini omap_dma_3_1, 4350d09e41aSPaolo Bonzini omap_dma_3_2, 4360d09e41aSPaolo Bonzini omap_dma_4, 4370d09e41aSPaolo Bonzini }; 4380d09e41aSPaolo Bonzini 4390d09e41aSPaolo Bonzini struct soc_dma_s; 4400d09e41aSPaolo Bonzini struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 4410d09e41aSPaolo Bonzini MemoryRegion *sysmem, 4420d09e41aSPaolo Bonzini qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 4430d09e41aSPaolo Bonzini enum omap_dma_model model); 4440d09e41aSPaolo Bonzini struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 4450d09e41aSPaolo Bonzini MemoryRegion *sysmem, 4460d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu, int fifo, 4470d09e41aSPaolo Bonzini int chans, omap_clk iclk, omap_clk fclk); 4480d09e41aSPaolo Bonzini void omap_dma_reset(struct soc_dma_s *s); 4490d09e41aSPaolo Bonzini 4500d09e41aSPaolo Bonzini struct dma_irq_map { 4510d09e41aSPaolo Bonzini int ih; 4520d09e41aSPaolo Bonzini int intr; 4530d09e41aSPaolo Bonzini }; 4540d09e41aSPaolo Bonzini 4550d09e41aSPaolo Bonzini /* Only used in OMAP DMA 3.x gigacells */ 4560d09e41aSPaolo Bonzini enum omap_dma_port { 4570d09e41aSPaolo Bonzini emiff = 0, 4580d09e41aSPaolo Bonzini emifs, 4590d09e41aSPaolo Bonzini imif, /* omap16xx: ocp_t1 */ 4600d09e41aSPaolo Bonzini tipb, 4610d09e41aSPaolo Bonzini local, /* omap16xx: ocp_t2 */ 4620d09e41aSPaolo Bonzini tipb_mpui, 4630d09e41aSPaolo Bonzini __omap_dma_port_last, 4640d09e41aSPaolo Bonzini }; 4650d09e41aSPaolo Bonzini 4660d09e41aSPaolo Bonzini typedef enum { 4670d09e41aSPaolo Bonzini constant = 0, 4680d09e41aSPaolo Bonzini post_incremented, 4690d09e41aSPaolo Bonzini single_index, 4700d09e41aSPaolo Bonzini double_index, 4710d09e41aSPaolo Bonzini } omap_dma_addressing_t; 4720d09e41aSPaolo Bonzini 4730d09e41aSPaolo Bonzini /* Only used in OMAP DMA 3.x gigacells */ 4740d09e41aSPaolo Bonzini struct omap_dma_lcd_channel_s { 4750d09e41aSPaolo Bonzini enum omap_dma_port src; 4760d09e41aSPaolo Bonzini hwaddr src_f1_top; 4770d09e41aSPaolo Bonzini hwaddr src_f1_bottom; 4780d09e41aSPaolo Bonzini hwaddr src_f2_top; 4790d09e41aSPaolo Bonzini hwaddr src_f2_bottom; 4800d09e41aSPaolo Bonzini 4810d09e41aSPaolo Bonzini /* Used in OMAP DMA 3.2 gigacell */ 4820d09e41aSPaolo Bonzini unsigned char brust_f1; 4830d09e41aSPaolo Bonzini unsigned char pack_f1; 4840d09e41aSPaolo Bonzini unsigned char data_type_f1; 4850d09e41aSPaolo Bonzini unsigned char brust_f2; 4860d09e41aSPaolo Bonzini unsigned char pack_f2; 4870d09e41aSPaolo Bonzini unsigned char data_type_f2; 4880d09e41aSPaolo Bonzini unsigned char end_prog; 4890d09e41aSPaolo Bonzini unsigned char repeat; 4900d09e41aSPaolo Bonzini unsigned char auto_init; 4910d09e41aSPaolo Bonzini unsigned char priority; 4920d09e41aSPaolo Bonzini unsigned char fs; 4930d09e41aSPaolo Bonzini unsigned char running; 4940d09e41aSPaolo Bonzini unsigned char bs; 4950d09e41aSPaolo Bonzini unsigned char omap_3_1_compatible_disable; 4960d09e41aSPaolo Bonzini unsigned char dst; 4970d09e41aSPaolo Bonzini unsigned char lch_type; 4980d09e41aSPaolo Bonzini int16_t element_index_f1; 4990d09e41aSPaolo Bonzini int16_t element_index_f2; 5000d09e41aSPaolo Bonzini int32_t frame_index_f1; 5010d09e41aSPaolo Bonzini int32_t frame_index_f2; 5020d09e41aSPaolo Bonzini uint16_t elements_f1; 5030d09e41aSPaolo Bonzini uint16_t frames_f1; 5040d09e41aSPaolo Bonzini uint16_t elements_f2; 5050d09e41aSPaolo Bonzini uint16_t frames_f2; 5060d09e41aSPaolo Bonzini omap_dma_addressing_t mode_f1; 5070d09e41aSPaolo Bonzini omap_dma_addressing_t mode_f2; 5080d09e41aSPaolo Bonzini 5090d09e41aSPaolo Bonzini /* Destination port is fixed. */ 5100d09e41aSPaolo Bonzini int interrupts; 5110d09e41aSPaolo Bonzini int condition; 5120d09e41aSPaolo Bonzini int dual; 5130d09e41aSPaolo Bonzini 5140d09e41aSPaolo Bonzini int current_frame; 5150d09e41aSPaolo Bonzini hwaddr phys_framebuffer[2]; 5160d09e41aSPaolo Bonzini qemu_irq irq; 5170d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu; 5180d09e41aSPaolo Bonzini } *omap_dma_get_lcdch(struct soc_dma_s *s); 5190d09e41aSPaolo Bonzini 5200d09e41aSPaolo Bonzini /* 5210d09e41aSPaolo Bonzini * DMA request numbers for OMAP1 5220d09e41aSPaolo Bonzini * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 5230d09e41aSPaolo Bonzini */ 5240d09e41aSPaolo Bonzini # define OMAP_DMA_NO_DEVICE 0 5250d09e41aSPaolo Bonzini # define OMAP_DMA_MCSI1_TX 1 5260d09e41aSPaolo Bonzini # define OMAP_DMA_MCSI1_RX 2 5270d09e41aSPaolo Bonzini # define OMAP_DMA_I2C_RX 3 5280d09e41aSPaolo Bonzini # define OMAP_DMA_I2C_TX 4 5290d09e41aSPaolo Bonzini # define OMAP_DMA_EXT_NDMA_REQ0 5 5300d09e41aSPaolo Bonzini # define OMAP_DMA_EXT_NDMA_REQ1 6 5310d09e41aSPaolo Bonzini # define OMAP_DMA_UWIRE_TX 7 5320d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP1_TX 8 5330d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP1_RX 9 5340d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP3_TX 10 5350d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP3_RX 11 5360d09e41aSPaolo Bonzini # define OMAP_DMA_UART1_TX 12 5370d09e41aSPaolo Bonzini # define OMAP_DMA_UART1_RX 13 5380d09e41aSPaolo Bonzini # define OMAP_DMA_UART2_TX 14 5390d09e41aSPaolo Bonzini # define OMAP_DMA_UART2_RX 15 5400d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP2_TX 16 5410d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP2_RX 17 5420d09e41aSPaolo Bonzini # define OMAP_DMA_UART3_TX 18 5430d09e41aSPaolo Bonzini # define OMAP_DMA_UART3_RX 19 5440d09e41aSPaolo Bonzini # define OMAP_DMA_CAMERA_IF_RX 20 5450d09e41aSPaolo Bonzini # define OMAP_DMA_MMC_TX 21 5460d09e41aSPaolo Bonzini # define OMAP_DMA_MMC_RX 22 5470d09e41aSPaolo Bonzini # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 5480d09e41aSPaolo Bonzini # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 5490d09e41aSPaolo Bonzini # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 5500d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX0 26 5510d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX1 27 5520d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX2 28 5530d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX0 29 5540d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX1 30 5550d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX2 31 5560d09e41aSPaolo Bonzini 5570d09e41aSPaolo Bonzini /* These are only for 1610 */ 5580d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_DES_IN 32 5590d09e41aSPaolo Bonzini # define OMAP_DMA_SPI_TX 33 5600d09e41aSPaolo Bonzini # define OMAP_DMA_SPI_RX 34 5610d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_HASH 35 5620d09e41aSPaolo Bonzini # define OMAP_DMA_CCP_ATTN 36 5630d09e41aSPaolo Bonzini # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 5640d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 5650d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 5660d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 5670d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 5680d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 5690d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 5700d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 5710d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 5720d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 5730d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 5740d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 5750d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 5760d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 5770d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 5780d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 5790d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 5800d09e41aSPaolo Bonzini # define OMAP_DMA_MMC2_TX 54 5810d09e41aSPaolo Bonzini # define OMAP_DMA_MMC2_RX 55 5820d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_DES_OUT 56 5830d09e41aSPaolo Bonzini 5840d09e41aSPaolo Bonzini /* 5850d09e41aSPaolo Bonzini * DMA request numbers for the OMAP2 5860d09e41aSPaolo Bonzini */ 5870d09e41aSPaolo Bonzini # define OMAP24XX_DMA_NO_DEVICE 0 5880d09e41aSPaolo Bonzini # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 5890d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ0 2 5900d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ1 3 5910d09e41aSPaolo Bonzini # define OMAP24XX_DMA_GPMC 4 5920d09e41aSPaolo Bonzini # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 5930d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DSS 6 5940d09e41aSPaolo Bonzini # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 5950d09e41aSPaolo Bonzini # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 5960d09e41aSPaolo Bonzini # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 5970d09e41aSPaolo Bonzini # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 5980d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 5990d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 6000d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 6010d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ2 14 6020d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ3 15 6030d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ4 16 6040d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_AC_RD 17 6050d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_AC_WR 18 6060d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_UL_RD 19 6070d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_UL_WR 20 6080d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_DL_RD 21 6090d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_DL_WR 22 6100d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_UL_RD 23 6110d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_UL_WR 24 6120d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_DL_RD 25 6130d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_DL_WR 26 6140d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C1_TX 27 6150d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C1_RX 28 6160d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C2_TX 29 6170d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C2_RX 30 6180d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP1_TX 31 6190d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP1_RX 32 6200d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP2_TX 33 6210d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP2_RX 34 6220d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX0 35 6230d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX0 36 6240d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX1 37 6250d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX1 38 6260d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX2 39 6270d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX2 40 6280d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX3 41 6290d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX3 42 6300d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_TX0 43 6310d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_RX0 44 6320d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_TX1 45 6330d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_RX1 46 6340d09e41aSPaolo Bonzini 6350d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART1_TX 49 6360d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART1_RX 50 6370d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART2_TX 51 6380d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART2_RX 52 6390d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART3_TX 53 6400d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART3_RX 54 6410d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX0 55 6420d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX0 56 6430d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX1 57 6440d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX1 58 6450d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX2 59 6460d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX2 60 6470d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MMC1_TX 61 6480d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MMC1_RX 62 6490d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 6500d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ5 64 6510d09e41aSPaolo Bonzini 6520d09e41aSPaolo Bonzini /* omap[123].c */ 6530d09e41aSPaolo Bonzini /* OMAP2 gp timer */ 6540d09e41aSPaolo Bonzini struct omap_gp_timer_s; 6550d09e41aSPaolo Bonzini struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 6560d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk); 6570d09e41aSPaolo Bonzini void omap_gp_timer_reset(struct omap_gp_timer_s *s); 6580d09e41aSPaolo Bonzini 6590d09e41aSPaolo Bonzini /* OMAP2 sysctimer */ 6600d09e41aSPaolo Bonzini struct omap_synctimer_s; 6610d09e41aSPaolo Bonzini struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 6620d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 6630d09e41aSPaolo Bonzini void omap_synctimer_reset(struct omap_synctimer_s *s); 6640d09e41aSPaolo Bonzini 6650d09e41aSPaolo Bonzini struct omap_uart_s; 6660d09e41aSPaolo Bonzini struct omap_uart_s *omap_uart_init(hwaddr base, 6670d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk, 6680d09e41aSPaolo Bonzini qemu_irq txdma, qemu_irq rxdma, 6690ec7b3e7SMarc-André Lureau const char *label, Chardev *chr); 6700d09e41aSPaolo Bonzini struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 6710d09e41aSPaolo Bonzini struct omap_target_agent_s *ta, 6720d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk, 6730d09e41aSPaolo Bonzini qemu_irq txdma, qemu_irq rxdma, 6740ec7b3e7SMarc-André Lureau const char *label, Chardev *chr); 6750d09e41aSPaolo Bonzini void omap_uart_reset(struct omap_uart_s *s); 6760ec7b3e7SMarc-André Lureau void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 6770d09e41aSPaolo Bonzini 6780d09e41aSPaolo Bonzini struct omap_mpuio_s; 6790d09e41aSPaolo Bonzini qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 6800d09e41aSPaolo Bonzini void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 6810d09e41aSPaolo Bonzini void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 6820d09e41aSPaolo Bonzini 6830d09e41aSPaolo Bonzini struct omap_uwire_s; 6840d09e41aSPaolo Bonzini void omap_uwire_attach(struct omap_uwire_s *s, 6850d09e41aSPaolo Bonzini uWireSlave *slave, int chipselect); 6860d09e41aSPaolo Bonzini 6870d09e41aSPaolo Bonzini /* OMAP2 spi */ 6880d09e41aSPaolo Bonzini struct omap_mcspi_s; 6890d09e41aSPaolo Bonzini struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 6900d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 6910d09e41aSPaolo Bonzini void omap_mcspi_attach(struct omap_mcspi_s *s, 6920d09e41aSPaolo Bonzini uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 6930d09e41aSPaolo Bonzini int chipselect); 6940d09e41aSPaolo Bonzini void omap_mcspi_reset(struct omap_mcspi_s *s); 6950d09e41aSPaolo Bonzini 6960d09e41aSPaolo Bonzini struct I2SCodec { 6970d09e41aSPaolo Bonzini void *opaque; 6980d09e41aSPaolo Bonzini 6990d09e41aSPaolo Bonzini /* The CPU can call this if it is generating the clock signal on the 7000d09e41aSPaolo Bonzini * i2s port. The CODEC can ignore it if it is set up as a clock 7010d09e41aSPaolo Bonzini * master and generates its own clock. */ 7020d09e41aSPaolo Bonzini void (*set_rate)(void *opaque, int in, int out); 7030d09e41aSPaolo Bonzini 7040d09e41aSPaolo Bonzini void (*tx_swallow)(void *opaque); 7050d09e41aSPaolo Bonzini qemu_irq rx_swallow; 7060d09e41aSPaolo Bonzini qemu_irq tx_start; 7070d09e41aSPaolo Bonzini 7080d09e41aSPaolo Bonzini int tx_rate; 7090d09e41aSPaolo Bonzini int cts; 7100d09e41aSPaolo Bonzini int rx_rate; 7110d09e41aSPaolo Bonzini int rts; 7120d09e41aSPaolo Bonzini 7130d09e41aSPaolo Bonzini struct i2s_fifo_s { 7140d09e41aSPaolo Bonzini uint8_t *fifo; 7150d09e41aSPaolo Bonzini int len; 7160d09e41aSPaolo Bonzini int start; 7170d09e41aSPaolo Bonzini int size; 7180d09e41aSPaolo Bonzini } in, out; 7190d09e41aSPaolo Bonzini }; 7200d09e41aSPaolo Bonzini struct omap_mcbsp_s; 7210d09e41aSPaolo Bonzini void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 7220d09e41aSPaolo Bonzini 7230d09e41aSPaolo Bonzini void omap_tap_init(struct omap_target_agent_s *ta, 7240d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu); 7250d09e41aSPaolo Bonzini 7260d09e41aSPaolo Bonzini /* omap_lcdc.c */ 7270d09e41aSPaolo Bonzini struct omap_lcd_panel_s; 7280d09e41aSPaolo Bonzini void omap_lcdc_reset(struct omap_lcd_panel_s *s); 7290d09e41aSPaolo Bonzini struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 7300d09e41aSPaolo Bonzini hwaddr base, 7310d09e41aSPaolo Bonzini qemu_irq irq, 7320d09e41aSPaolo Bonzini struct omap_dma_lcd_channel_s *dma, 7330d09e41aSPaolo Bonzini omap_clk clk); 7340d09e41aSPaolo Bonzini 7350d09e41aSPaolo Bonzini /* omap_dss.c */ 7360d09e41aSPaolo Bonzini struct rfbi_chip_s { 7370d09e41aSPaolo Bonzini void *opaque; 7380d09e41aSPaolo Bonzini void (*write)(void *opaque, int dc, uint16_t value); 7390d09e41aSPaolo Bonzini void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 7400d09e41aSPaolo Bonzini uint16_t (*read)(void *opaque, int dc); 7410d09e41aSPaolo Bonzini }; 7420d09e41aSPaolo Bonzini struct omap_dss_s; 7430d09e41aSPaolo Bonzini void omap_dss_reset(struct omap_dss_s *s); 7440d09e41aSPaolo Bonzini struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 7450d09e41aSPaolo Bonzini MemoryRegion *sysmem, 7460d09e41aSPaolo Bonzini hwaddr l3_base, 7470d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq drq, 7480d09e41aSPaolo Bonzini omap_clk fck1, omap_clk fck2, omap_clk ck54m, 7490d09e41aSPaolo Bonzini omap_clk ick1, omap_clk ick2); 7500d09e41aSPaolo Bonzini void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 7510d09e41aSPaolo Bonzini 7520d09e41aSPaolo Bonzini /* omap_mmc.c */ 7530d09e41aSPaolo Bonzini struct omap_mmc_s; 7540d09e41aSPaolo Bonzini struct omap_mmc_s *omap_mmc_init(hwaddr base, 7550d09e41aSPaolo Bonzini MemoryRegion *sysmem, 7564be74634SMarkus Armbruster BlockBackend *blk, 7570d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq dma[], omap_clk clk); 7580d09e41aSPaolo Bonzini struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 7594be74634SMarkus Armbruster BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 7600d09e41aSPaolo Bonzini omap_clk fclk, omap_clk iclk); 7610d09e41aSPaolo Bonzini void omap_mmc_reset(struct omap_mmc_s *s); 7620d09e41aSPaolo Bonzini void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 7630d09e41aSPaolo Bonzini void omap_mmc_enable(struct omap_mmc_s *s, int enable); 7640d09e41aSPaolo Bonzini 7650d09e41aSPaolo Bonzini /* omap_i2c.c */ 766a5c82852SAndreas Färber I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 7670d09e41aSPaolo Bonzini 7680d09e41aSPaolo Bonzini # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 7690d09e41aSPaolo Bonzini # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 7700d09e41aSPaolo Bonzini # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 7710d09e41aSPaolo Bonzini # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 7720d09e41aSPaolo Bonzini # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 7730d09e41aSPaolo Bonzini # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 7740d09e41aSPaolo Bonzini # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 7750d09e41aSPaolo Bonzini # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 7760d09e41aSPaolo Bonzini # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 7770d09e41aSPaolo Bonzini 7780d09e41aSPaolo Bonzini # define cpu_is_omap15xx(cpu) \ 7790d09e41aSPaolo Bonzini (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 7800d09e41aSPaolo Bonzini # define cpu_is_omap16xx(cpu) \ 7810d09e41aSPaolo Bonzini (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 7820d09e41aSPaolo Bonzini # define cpu_is_omap24xx(cpu) \ 7830d09e41aSPaolo Bonzini (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 7840d09e41aSPaolo Bonzini 7850d09e41aSPaolo Bonzini # define cpu_class_omap1(cpu) \ 7860d09e41aSPaolo Bonzini (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 7870d09e41aSPaolo Bonzini # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 7880d09e41aSPaolo Bonzini # define cpu_class_omap3(cpu) \ 7890d09e41aSPaolo Bonzini (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 7900d09e41aSPaolo Bonzini 7910d09e41aSPaolo Bonzini struct omap_mpu_state_s { 7920d09e41aSPaolo Bonzini enum omap_mpu_model { 7930d09e41aSPaolo Bonzini omap310, 7940d09e41aSPaolo Bonzini omap1510, 7950d09e41aSPaolo Bonzini omap1610, 7960d09e41aSPaolo Bonzini omap1710, 7970d09e41aSPaolo Bonzini omap2410, 7980d09e41aSPaolo Bonzini omap2420, 7990d09e41aSPaolo Bonzini omap2422, 8000d09e41aSPaolo Bonzini omap2423, 8010d09e41aSPaolo Bonzini omap2430, 8020d09e41aSPaolo Bonzini omap3430, 8030d09e41aSPaolo Bonzini omap3630, 8040d09e41aSPaolo Bonzini } mpu_model; 8050d09e41aSPaolo Bonzini 8060d09e41aSPaolo Bonzini ARMCPU *cpu; 8070d09e41aSPaolo Bonzini 8080d09e41aSPaolo Bonzini qemu_irq *drq; 8090d09e41aSPaolo Bonzini 8100d09e41aSPaolo Bonzini qemu_irq wakeup; 8110d09e41aSPaolo Bonzini 8120d09e41aSPaolo Bonzini MemoryRegion ulpd_pm_iomem; 8130d09e41aSPaolo Bonzini MemoryRegion pin_cfg_iomem; 8140d09e41aSPaolo Bonzini MemoryRegion id_iomem; 8150d09e41aSPaolo Bonzini MemoryRegion id_iomem_e18; 8160d09e41aSPaolo Bonzini MemoryRegion id_iomem_ed4; 8170d09e41aSPaolo Bonzini MemoryRegion id_iomem_e20; 8180d09e41aSPaolo Bonzini MemoryRegion mpui_iomem; 8190d09e41aSPaolo Bonzini MemoryRegion tcmi_iomem; 8200d09e41aSPaolo Bonzini MemoryRegion clkm_iomem; 8210d09e41aSPaolo Bonzini MemoryRegion clkdsp_iomem; 8220d09e41aSPaolo Bonzini MemoryRegion mpui_io_iomem; 8230d09e41aSPaolo Bonzini MemoryRegion tap_iomem; 8240d09e41aSPaolo Bonzini MemoryRegion imif_ram; 8250d09e41aSPaolo Bonzini MemoryRegion emiff_ram; 8260d09e41aSPaolo Bonzini MemoryRegion sdram; 8270d09e41aSPaolo Bonzini MemoryRegion sram; 8280d09e41aSPaolo Bonzini 8290d09e41aSPaolo Bonzini struct omap_dma_port_if_s { 8300d09e41aSPaolo Bonzini uint32_t (*read[3])(struct omap_mpu_state_s *s, 8310d09e41aSPaolo Bonzini hwaddr offset); 8320d09e41aSPaolo Bonzini void (*write[3])(struct omap_mpu_state_s *s, 8330d09e41aSPaolo Bonzini hwaddr offset, uint32_t value); 8340d09e41aSPaolo Bonzini int (*addr_valid)(struct omap_mpu_state_s *s, 8350d09e41aSPaolo Bonzini hwaddr addr); 8360d09e41aSPaolo Bonzini } port[__omap_dma_port_last]; 8370d09e41aSPaolo Bonzini 8380d09e41aSPaolo Bonzini unsigned long sdram_size; 8390d09e41aSPaolo Bonzini unsigned long sram_size; 8400d09e41aSPaolo Bonzini 8410d09e41aSPaolo Bonzini /* MPUI-TIPB peripherals */ 8420d09e41aSPaolo Bonzini struct omap_uart_s *uart[3]; 8430d09e41aSPaolo Bonzini 8440d09e41aSPaolo Bonzini DeviceState *gpio; 8450d09e41aSPaolo Bonzini 8460d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp1; 8470d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp3; 8480d09e41aSPaolo Bonzini 8490d09e41aSPaolo Bonzini /* MPU public TIPB peripherals */ 8500d09e41aSPaolo Bonzini struct omap_32khz_timer_s *os_timer; 8510d09e41aSPaolo Bonzini 8520d09e41aSPaolo Bonzini struct omap_mmc_s *mmc; 8530d09e41aSPaolo Bonzini 8540d09e41aSPaolo Bonzini struct omap_mpuio_s *mpuio; 8550d09e41aSPaolo Bonzini 8560d09e41aSPaolo Bonzini struct omap_uwire_s *microwire; 8570d09e41aSPaolo Bonzini 8580d09e41aSPaolo Bonzini struct omap_pwl_s *pwl; 8590d09e41aSPaolo Bonzini struct omap_pwt_s *pwt; 8600d09e41aSPaolo Bonzini DeviceState *i2c[2]; 8610d09e41aSPaolo Bonzini 8620d09e41aSPaolo Bonzini struct omap_rtc_s *rtc; 8630d09e41aSPaolo Bonzini 8640d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp2; 8650d09e41aSPaolo Bonzini 8660d09e41aSPaolo Bonzini struct omap_lpg_s *led[2]; 8670d09e41aSPaolo Bonzini 8680d09e41aSPaolo Bonzini /* MPU private TIPB peripherals */ 8690d09e41aSPaolo Bonzini DeviceState *ih[2]; 8700d09e41aSPaolo Bonzini 8710d09e41aSPaolo Bonzini struct soc_dma_s *dma; 8720d09e41aSPaolo Bonzini 8730d09e41aSPaolo Bonzini struct omap_mpu_timer_s *timer[3]; 8740d09e41aSPaolo Bonzini struct omap_watchdog_timer_s *wdt; 8750d09e41aSPaolo Bonzini 8760d09e41aSPaolo Bonzini struct omap_lcd_panel_s *lcd; 8770d09e41aSPaolo Bonzini 8780d09e41aSPaolo Bonzini uint32_t ulpd_pm_regs[21]; 8790d09e41aSPaolo Bonzini int64_t ulpd_gauge_start; 8800d09e41aSPaolo Bonzini 8810d09e41aSPaolo Bonzini uint32_t func_mux_ctrl[14]; 8820d09e41aSPaolo Bonzini uint32_t comp_mode_ctrl[1]; 8830d09e41aSPaolo Bonzini uint32_t pull_dwn_ctrl[4]; 8840d09e41aSPaolo Bonzini uint32_t gate_inh_ctrl[1]; 8850d09e41aSPaolo Bonzini uint32_t voltage_ctrl[1]; 8860d09e41aSPaolo Bonzini uint32_t test_dbg_ctrl[1]; 8870d09e41aSPaolo Bonzini uint32_t mod_conf_ctrl[1]; 8880d09e41aSPaolo Bonzini int compat1509; 8890d09e41aSPaolo Bonzini 8900d09e41aSPaolo Bonzini uint32_t mpui_ctrl; 8910d09e41aSPaolo Bonzini 8920d09e41aSPaolo Bonzini struct omap_tipb_bridge_s *private_tipb; 8930d09e41aSPaolo Bonzini struct omap_tipb_bridge_s *public_tipb; 8940d09e41aSPaolo Bonzini 8950d09e41aSPaolo Bonzini uint32_t tcmi_regs[17]; 8960d09e41aSPaolo Bonzini 8970d09e41aSPaolo Bonzini struct dpll_ctl_s *dpll[3]; 8980d09e41aSPaolo Bonzini 8990d09e41aSPaolo Bonzini omap_clk clks; 9000d09e41aSPaolo Bonzini struct { 9010d09e41aSPaolo Bonzini int cold_start; 9020d09e41aSPaolo Bonzini int clocking_scheme; 9030d09e41aSPaolo Bonzini uint16_t arm_ckctl; 9040d09e41aSPaolo Bonzini uint16_t arm_idlect1; 9050d09e41aSPaolo Bonzini uint16_t arm_idlect2; 9060d09e41aSPaolo Bonzini uint16_t arm_ewupct; 9070d09e41aSPaolo Bonzini uint16_t arm_rstct1; 9080d09e41aSPaolo Bonzini uint16_t arm_rstct2; 9090d09e41aSPaolo Bonzini uint16_t arm_ckout1; 9100d09e41aSPaolo Bonzini int dpll1_mode; 9110d09e41aSPaolo Bonzini uint16_t dsp_idlect1; 9120d09e41aSPaolo Bonzini uint16_t dsp_idlect2; 9130d09e41aSPaolo Bonzini uint16_t dsp_rstct2; 9140d09e41aSPaolo Bonzini } clkm; 9150d09e41aSPaolo Bonzini 9160d09e41aSPaolo Bonzini /* OMAP2-only peripherals */ 9170d09e41aSPaolo Bonzini struct omap_l4_s *l4; 9180d09e41aSPaolo Bonzini 9190d09e41aSPaolo Bonzini struct omap_gp_timer_s *gptimer[12]; 9200d09e41aSPaolo Bonzini struct omap_synctimer_s *synctimer; 9210d09e41aSPaolo Bonzini 9220d09e41aSPaolo Bonzini struct omap_prcm_s *prcm; 9230d09e41aSPaolo Bonzini struct omap_sdrc_s *sdrc; 9240d09e41aSPaolo Bonzini struct omap_gpmc_s *gpmc; 9250d09e41aSPaolo Bonzini struct omap_sysctl_s *sysc; 9260d09e41aSPaolo Bonzini 9270d09e41aSPaolo Bonzini struct omap_mcspi_s *mcspi[2]; 9280d09e41aSPaolo Bonzini 9290d09e41aSPaolo Bonzini struct omap_dss_s *dss; 9300d09e41aSPaolo Bonzini 9310d09e41aSPaolo Bonzini struct omap_eac_s *eac; 9320d09e41aSPaolo Bonzini }; 9330d09e41aSPaolo Bonzini 9340d09e41aSPaolo Bonzini /* omap1.c */ 9350d09e41aSPaolo Bonzini struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 9360d09e41aSPaolo Bonzini unsigned long sdram_size, 9370d09e41aSPaolo Bonzini const char *core); 9380d09e41aSPaolo Bonzini 9390d09e41aSPaolo Bonzini /* omap2.c */ 9400d09e41aSPaolo Bonzini struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 9410d09e41aSPaolo Bonzini unsigned long sdram_size, 9420d09e41aSPaolo Bonzini const char *core); 9430d09e41aSPaolo Bonzini 9440d09e41aSPaolo Bonzini uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 9450d09e41aSPaolo Bonzini void omap_badwidth_write8(void *opaque, hwaddr addr, 9460d09e41aSPaolo Bonzini uint32_t value); 9470d09e41aSPaolo Bonzini uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 9480d09e41aSPaolo Bonzini void omap_badwidth_write16(void *opaque, hwaddr addr, 9490d09e41aSPaolo Bonzini uint32_t value); 9500d09e41aSPaolo Bonzini uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 9510d09e41aSPaolo Bonzini void omap_badwidth_write32(void *opaque, hwaddr addr, 9520d09e41aSPaolo Bonzini uint32_t value); 9530d09e41aSPaolo Bonzini 9540d09e41aSPaolo Bonzini void omap_mpu_wakeup(void *opaque, int irq, int req); 9550d09e41aSPaolo Bonzini 9560d09e41aSPaolo Bonzini # define OMAP_BAD_REG(paddr) \ 95784b335c6SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 958a89f364aSAlistair Francis __func__, paddr) 9590d09e41aSPaolo Bonzini # define OMAP_RO_REG(paddr) \ 96084b335c6SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 96184b335c6SPhilippe Mathieu-Daudé HWADDR_PRIx "\n", \ 962a89f364aSAlistair Francis __func__, paddr) 9630d09e41aSPaolo Bonzini 9640d09e41aSPaolo Bonzini /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 9650d09e41aSPaolo Bonzini (Board-specifc tags are not here) */ 9660d09e41aSPaolo Bonzini #define OMAP_TAG_CLOCK 0x4f01 9670d09e41aSPaolo Bonzini #define OMAP_TAG_MMC 0x4f02 9680d09e41aSPaolo Bonzini #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 9690d09e41aSPaolo Bonzini #define OMAP_TAG_USB 0x4f04 9700d09e41aSPaolo Bonzini #define OMAP_TAG_LCD 0x4f05 9710d09e41aSPaolo Bonzini #define OMAP_TAG_GPIO_SWITCH 0x4f06 9720d09e41aSPaolo Bonzini #define OMAP_TAG_UART 0x4f07 9730d09e41aSPaolo Bonzini #define OMAP_TAG_FBMEM 0x4f08 9740d09e41aSPaolo Bonzini #define OMAP_TAG_STI_CONSOLE 0x4f09 9750d09e41aSPaolo Bonzini #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 9760d09e41aSPaolo Bonzini #define OMAP_TAG_PARTITION 0x4f0b 9770d09e41aSPaolo Bonzini #define OMAP_TAG_TEA5761 0x4f10 9780d09e41aSPaolo Bonzini #define OMAP_TAG_TMP105 0x4f11 9790d09e41aSPaolo Bonzini #define OMAP_TAG_BOOT_REASON 0x4f80 9800d09e41aSPaolo Bonzini #define OMAP_TAG_FLASH_PART_STR 0x4f81 9810d09e41aSPaolo Bonzini #define OMAP_TAG_VERSION_STR 0x4f82 9820d09e41aSPaolo Bonzini 9830d09e41aSPaolo Bonzini enum { 9840d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_COVER = 0 << 4, 9850d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 9860d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 9870d09e41aSPaolo Bonzini }; 9880d09e41aSPaolo Bonzini 9890d09e41aSPaolo Bonzini #define OMAP_GPIOSW_INVERTED 0x0001 9900d09e41aSPaolo Bonzini #define OMAP_GPIOSW_OUTPUT 0x0002 9910d09e41aSPaolo Bonzini 9920d09e41aSPaolo Bonzini # define OMAP_MPUI_REG_MASK 0x000007ff 9930d09e41aSPaolo Bonzini 9940d09e41aSPaolo Bonzini #endif /* hw_omap_h */ 995