1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/cpu/a9mpcore.h" 21 #include "hw/mem/npcm7xx_mc.h" 22 #include "hw/misc/npcm7xx_clk.h" 23 #include "hw/misc/npcm7xx_gcr.h" 24 #include "hw/nvram/npcm7xx_otp.h" 25 #include "hw/timer/npcm7xx_timer.h" 26 #include "hw/ssi/npcm7xx_fiu.h" 27 #include "target/arm/cpu.h" 28 29 #define NPCM7XX_MAX_NUM_CPUS (2) 30 31 /* The first half of the address space is reserved for DDR4 DRAM. */ 32 #define NPCM7XX_DRAM_BA (0x00000000) 33 #define NPCM7XX_DRAM_SZ (2 * GiB) 34 35 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 36 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 37 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 38 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 39 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 40 41 typedef struct NPCM7xxMachine { 42 MachineState parent; 43 } NPCM7xxMachine; 44 45 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 46 #define NPCM7XX_MACHINE(obj) \ 47 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 48 49 typedef struct NPCM7xxMachineClass { 50 MachineClass parent; 51 52 const char *soc_type; 53 } NPCM7xxMachineClass; 54 55 #define NPCM7XX_MACHINE_CLASS(klass) \ 56 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 57 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 58 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 59 60 typedef struct NPCM7xxState { 61 DeviceState parent; 62 63 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 64 A9MPPrivState a9mpcore; 65 66 MemoryRegion sram; 67 MemoryRegion irom; 68 MemoryRegion ram3; 69 MemoryRegion *dram; 70 71 NPCM7xxGCRState gcr; 72 NPCM7xxCLKState clk; 73 NPCM7xxTimerCtrlState tim[3]; 74 NPCM7xxOTPState key_storage; 75 NPCM7xxOTPState fuse_array; 76 NPCM7xxMCState mc; 77 NPCM7xxFIUState fiu[2]; 78 } NPCM7xxState; 79 80 #define TYPE_NPCM7XX "npcm7xx" 81 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 82 83 #define TYPE_NPCM730 "npcm730" 84 #define TYPE_NPCM750 "npcm750" 85 86 typedef struct NPCM7xxClass { 87 DeviceClass parent; 88 89 /* Bitmask of modules that are permanently disabled on this chip. */ 90 uint32_t disabled_modules; 91 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 92 uint32_t num_cpus; 93 } NPCM7xxClass; 94 95 #define NPCM7XX_CLASS(klass) \ 96 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 97 #define NPCM7XX_GET_CLASS(obj) \ 98 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 99 100 /** 101 * npcm7xx_load_kernel - Loads memory with everything needed to boot 102 * @machine - The machine containing the SoC to be booted. 103 * @soc - The SoC containing the CPU to be booted. 104 * 105 * This will set up the ARM boot info structure for the specific NPCM7xx 106 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 107 * into memory, if requested by the user. 108 */ 109 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 110 111 #endif /* NPCM7XX_H */ 112