1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/cpu/a9mpcore.h" 21 #include "hw/mem/npcm7xx_mc.h" 22 #include "hw/misc/npcm7xx_clk.h" 23 #include "hw/misc/npcm7xx_gcr.h" 24 #include "hw/nvram/npcm7xx_otp.h" 25 #include "hw/timer/npcm7xx_timer.h" 26 #include "hw/ssi/npcm7xx_fiu.h" 27 #include "target/arm/cpu.h" 28 29 #define NPCM7XX_MAX_NUM_CPUS (2) 30 31 /* The first half of the address space is reserved for DDR4 DRAM. */ 32 #define NPCM7XX_DRAM_BA (0x00000000) 33 #define NPCM7XX_DRAM_SZ (2 * GiB) 34 35 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 36 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 37 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 38 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 39 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 40 #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ 41 42 typedef struct NPCM7xxMachine { 43 MachineState parent; 44 } NPCM7xxMachine; 45 46 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 47 #define NPCM7XX_MACHINE(obj) \ 48 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 49 50 typedef struct NPCM7xxMachineClass { 51 MachineClass parent; 52 53 const char *soc_type; 54 } NPCM7xxMachineClass; 55 56 #define NPCM7XX_MACHINE_CLASS(klass) \ 57 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 58 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 59 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 60 61 typedef struct NPCM7xxState { 62 DeviceState parent; 63 64 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 65 A9MPPrivState a9mpcore; 66 67 MemoryRegion sram; 68 MemoryRegion irom; 69 MemoryRegion ram3; 70 MemoryRegion *dram; 71 72 NPCM7xxGCRState gcr; 73 NPCM7xxCLKState clk; 74 NPCM7xxTimerCtrlState tim[3]; 75 NPCM7xxOTPState key_storage; 76 NPCM7xxOTPState fuse_array; 77 NPCM7xxMCState mc; 78 NPCM7xxFIUState fiu[2]; 79 } NPCM7xxState; 80 81 #define TYPE_NPCM7XX "npcm7xx" 82 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 83 84 #define TYPE_NPCM730 "npcm730" 85 #define TYPE_NPCM750 "npcm750" 86 87 typedef struct NPCM7xxClass { 88 DeviceClass parent; 89 90 /* Bitmask of modules that are permanently disabled on this chip. */ 91 uint32_t disabled_modules; 92 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 93 uint32_t num_cpus; 94 } NPCM7xxClass; 95 96 #define NPCM7XX_CLASS(klass) \ 97 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 98 #define NPCM7XX_GET_CLASS(obj) \ 99 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 100 101 /** 102 * npcm7xx_load_kernel - Loads memory with everything needed to boot 103 * @machine - The machine containing the SoC to be booted. 104 * @soc - The SoC containing the CPU to be booted. 105 * 106 * This will set up the ARM boot info structure for the specific NPCM7xx 107 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 108 * into memory, if requested by the user. 109 */ 110 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 111 112 #endif /* NPCM7XX_H */ 113