1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/adc/npcm7xx_adc.h" 21 #include "hw/cpu/a9mpcore.h" 22 #include "hw/gpio/npcm7xx_gpio.h" 23 #include "hw/mem/npcm7xx_mc.h" 24 #include "hw/misc/npcm7xx_clk.h" 25 #include "hw/misc/npcm7xx_gcr.h" 26 #include "hw/misc/npcm7xx_pwm.h" 27 #include "hw/misc/npcm7xx_rng.h" 28 #include "hw/nvram/npcm7xx_otp.h" 29 #include "hw/timer/npcm7xx_timer.h" 30 #include "hw/ssi/npcm7xx_fiu.h" 31 #include "hw/usb/hcd-ehci.h" 32 #include "hw/usb/hcd-ohci.h" 33 #include "target/arm/cpu.h" 34 35 #define NPCM7XX_MAX_NUM_CPUS (2) 36 37 /* The first half of the address space is reserved for DDR4 DRAM. */ 38 #define NPCM7XX_DRAM_BA (0x00000000) 39 #define NPCM7XX_DRAM_SZ (2 * GiB) 40 41 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 42 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 43 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 44 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 45 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 46 #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ 47 48 typedef struct NPCM7xxMachine { 49 MachineState parent; 50 } NPCM7xxMachine; 51 52 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 53 #define NPCM7XX_MACHINE(obj) \ 54 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 55 56 typedef struct NPCM7xxMachineClass { 57 MachineClass parent; 58 59 const char *soc_type; 60 } NPCM7xxMachineClass; 61 62 #define NPCM7XX_MACHINE_CLASS(klass) \ 63 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 64 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 65 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 66 67 typedef struct NPCM7xxState { 68 DeviceState parent; 69 70 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 71 A9MPPrivState a9mpcore; 72 73 MemoryRegion sram; 74 MemoryRegion irom; 75 MemoryRegion ram3; 76 MemoryRegion *dram; 77 78 NPCM7xxGCRState gcr; 79 NPCM7xxCLKState clk; 80 NPCM7xxTimerCtrlState tim[3]; 81 NPCM7xxADCState adc; 82 NPCM7xxPWMState pwm[2]; 83 NPCM7xxOTPState key_storage; 84 NPCM7xxOTPState fuse_array; 85 NPCM7xxMCState mc; 86 NPCM7xxRNGState rng; 87 NPCM7xxGPIOState gpio[8]; 88 EHCISysBusState ehci; 89 OHCISysBusState ohci; 90 NPCM7xxFIUState fiu[2]; 91 } NPCM7xxState; 92 93 #define TYPE_NPCM7XX "npcm7xx" 94 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 95 96 #define TYPE_NPCM730 "npcm730" 97 #define TYPE_NPCM750 "npcm750" 98 99 typedef struct NPCM7xxClass { 100 DeviceClass parent; 101 102 /* Bitmask of modules that are permanently disabled on this chip. */ 103 uint32_t disabled_modules; 104 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 105 uint32_t num_cpus; 106 } NPCM7xxClass; 107 108 #define NPCM7XX_CLASS(klass) \ 109 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 110 #define NPCM7XX_GET_CLASS(obj) \ 111 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 112 113 /** 114 * npcm7xx_load_kernel - Loads memory with everything needed to boot 115 * @machine - The machine containing the SoC to be booted. 116 * @soc - The SoC containing the CPU to be booted. 117 * 118 * This will set up the ARM boot info structure for the specific NPCM7xx 119 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 120 * into memory, if requested by the user. 121 */ 122 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 123 124 #endif /* NPCM7XX_H */ 125