1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/cpu/a9mpcore.h" 21 #include "hw/mem/npcm7xx_mc.h" 22 #include "hw/misc/npcm7xx_clk.h" 23 #include "hw/misc/npcm7xx_gcr.h" 24 #include "hw/misc/npcm7xx_rng.h" 25 #include "hw/nvram/npcm7xx_otp.h" 26 #include "hw/timer/npcm7xx_timer.h" 27 #include "hw/ssi/npcm7xx_fiu.h" 28 #include "target/arm/cpu.h" 29 30 #define NPCM7XX_MAX_NUM_CPUS (2) 31 32 /* The first half of the address space is reserved for DDR4 DRAM. */ 33 #define NPCM7XX_DRAM_BA (0x00000000) 34 #define NPCM7XX_DRAM_SZ (2 * GiB) 35 36 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 37 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 38 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 39 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 40 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 41 #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ 42 43 typedef struct NPCM7xxMachine { 44 MachineState parent; 45 } NPCM7xxMachine; 46 47 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 48 #define NPCM7XX_MACHINE(obj) \ 49 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 50 51 typedef struct NPCM7xxMachineClass { 52 MachineClass parent; 53 54 const char *soc_type; 55 } NPCM7xxMachineClass; 56 57 #define NPCM7XX_MACHINE_CLASS(klass) \ 58 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 59 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 60 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 61 62 typedef struct NPCM7xxState { 63 DeviceState parent; 64 65 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 66 A9MPPrivState a9mpcore; 67 68 MemoryRegion sram; 69 MemoryRegion irom; 70 MemoryRegion ram3; 71 MemoryRegion *dram; 72 73 NPCM7xxGCRState gcr; 74 NPCM7xxCLKState clk; 75 NPCM7xxTimerCtrlState tim[3]; 76 NPCM7xxOTPState key_storage; 77 NPCM7xxOTPState fuse_array; 78 NPCM7xxMCState mc; 79 NPCM7xxRNGState rng; 80 NPCM7xxFIUState fiu[2]; 81 } NPCM7xxState; 82 83 #define TYPE_NPCM7XX "npcm7xx" 84 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 85 86 #define TYPE_NPCM730 "npcm730" 87 #define TYPE_NPCM750 "npcm750" 88 89 typedef struct NPCM7xxClass { 90 DeviceClass parent; 91 92 /* Bitmask of modules that are permanently disabled on this chip. */ 93 uint32_t disabled_modules; 94 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 95 uint32_t num_cpus; 96 } NPCM7xxClass; 97 98 #define NPCM7XX_CLASS(klass) \ 99 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 100 #define NPCM7XX_GET_CLASS(obj) \ 101 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 102 103 /** 104 * npcm7xx_load_kernel - Loads memory with everything needed to boot 105 * @machine - The machine containing the SoC to be booted. 106 * @soc - The SoC containing the CPU to be booted. 107 * 108 * This will set up the ARM boot info structure for the specific NPCM7xx 109 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 110 * into memory, if requested by the user. 111 */ 112 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 113 114 #endif /* NPCM7XX_H */ 115