1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/adc/npcm7xx_adc.h" 21 #include "hw/cpu/a9mpcore.h" 22 #include "hw/gpio/npcm7xx_gpio.h" 23 #include "hw/i2c/npcm7xx_smbus.h" 24 #include "hw/mem/npcm7xx_mc.h" 25 #include "hw/misc/npcm7xx_clk.h" 26 #include "hw/misc/npcm7xx_gcr.h" 27 #include "hw/misc/npcm7xx_pwm.h" 28 #include "hw/misc/npcm7xx_rng.h" 29 #include "hw/nvram/npcm7xx_otp.h" 30 #include "hw/timer/npcm7xx_timer.h" 31 #include "hw/ssi/npcm7xx_fiu.h" 32 #include "hw/usb/hcd-ehci.h" 33 #include "hw/usb/hcd-ohci.h" 34 #include "target/arm/cpu.h" 35 36 #define NPCM7XX_MAX_NUM_CPUS (2) 37 38 /* The first half of the address space is reserved for DDR4 DRAM. */ 39 #define NPCM7XX_DRAM_BA (0x00000000) 40 #define NPCM7XX_DRAM_SZ (2 * GiB) 41 42 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 43 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 44 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 45 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 46 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 47 #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ 48 49 typedef struct NPCM7xxMachine { 50 MachineState parent; 51 } NPCM7xxMachine; 52 53 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 54 #define NPCM7XX_MACHINE(obj) \ 55 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 56 57 typedef struct NPCM7xxMachineClass { 58 MachineClass parent; 59 60 const char *soc_type; 61 } NPCM7xxMachineClass; 62 63 #define NPCM7XX_MACHINE_CLASS(klass) \ 64 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 65 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 66 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 67 68 typedef struct NPCM7xxState { 69 DeviceState parent; 70 71 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 72 A9MPPrivState a9mpcore; 73 74 MemoryRegion sram; 75 MemoryRegion irom; 76 MemoryRegion ram3; 77 MemoryRegion *dram; 78 79 NPCM7xxGCRState gcr; 80 NPCM7xxCLKState clk; 81 NPCM7xxTimerCtrlState tim[3]; 82 NPCM7xxADCState adc; 83 NPCM7xxPWMState pwm[2]; 84 NPCM7xxOTPState key_storage; 85 NPCM7xxOTPState fuse_array; 86 NPCM7xxMCState mc; 87 NPCM7xxRNGState rng; 88 NPCM7xxGPIOState gpio[8]; 89 NPCM7xxSMBusState smbus[16]; 90 EHCISysBusState ehci; 91 OHCISysBusState ohci; 92 NPCM7xxFIUState fiu[2]; 93 } NPCM7xxState; 94 95 #define TYPE_NPCM7XX "npcm7xx" 96 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 97 98 #define TYPE_NPCM730 "npcm730" 99 #define TYPE_NPCM750 "npcm750" 100 101 typedef struct NPCM7xxClass { 102 DeviceClass parent; 103 104 /* Bitmask of modules that are permanently disabled on this chip. */ 105 uint32_t disabled_modules; 106 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 107 uint32_t num_cpus; 108 } NPCM7xxClass; 109 110 #define NPCM7XX_CLASS(klass) \ 111 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 112 #define NPCM7XX_GET_CLASS(obj) \ 113 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 114 115 /** 116 * npcm7xx_load_kernel - Loads memory with everything needed to boot 117 * @machine - The machine containing the SoC to be booted. 118 * @soc - The SoC containing the CPU to be booted. 119 * 120 * This will set up the ARM boot info structure for the specific NPCM7xx 121 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 122 * into memory, if requested by the user. 123 */ 124 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 125 126 #endif /* NPCM7XX_H */ 127