1 /* 2 * MAX78000 SOC 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef HW_ARM_MAX78000_SOC_H 10 #define HW_ARM_MAX78000_SOC_H 11 12 #include "hw/or-irq.h" 13 #include "hw/arm/armv7m.h" 14 #include "hw/misc/max78000_gcr.h" 15 #include "hw/misc/max78000_icc.h" 16 #include "hw/char/max78000_uart.h" 17 #include "qom/object.h" 18 19 #define TYPE_MAX78000_SOC "max78000-soc" 20 OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) 21 22 #define FLASH_BASE_ADDRESS 0x10000000 23 #define FLASH_SIZE (512 * 1024) 24 #define SRAM_BASE_ADDRESS 0x20000000 25 #define SRAM_SIZE (128 * 1024) 26 27 /* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */ 28 #define MAX78000_NUM_ICC 2 29 #define MAX78000_NUM_UART 3 30 31 struct MAX78000State { 32 SysBusDevice parent_obj; 33 34 ARMv7MState armv7m; 35 36 MemoryRegion sram; 37 MemoryRegion flash; 38 39 Max78000GcrState gcr; 40 Max78000IccState icc[MAX78000_NUM_ICC]; 41 Max78000UartState uart[MAX78000_NUM_UART]; 42 43 Clock *sysclk; 44 }; 45 46 #endif 47