151eb283dSJackson Donaldson /* 251eb283dSJackson Donaldson * MAX78000 SOC 351eb283dSJackson Donaldson * 451eb283dSJackson Donaldson * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 551eb283dSJackson Donaldson * 651eb283dSJackson Donaldson * SPDX-License-Identifier: GPL-2.0-or-later 751eb283dSJackson Donaldson */ 851eb283dSJackson Donaldson 951eb283dSJackson Donaldson #ifndef HW_ARM_MAX78000_SOC_H 1051eb283dSJackson Donaldson #define HW_ARM_MAX78000_SOC_H 1151eb283dSJackson Donaldson 1251eb283dSJackson Donaldson #include "hw/or-irq.h" 1351eb283dSJackson Donaldson #include "hw/arm/armv7m.h" 14*65714d3eSJackson Donaldson #include "hw/misc/max78000_icc.h" 1551eb283dSJackson Donaldson #include "qom/object.h" 1651eb283dSJackson Donaldson 1751eb283dSJackson Donaldson #define TYPE_MAX78000_SOC "max78000-soc" 1851eb283dSJackson Donaldson OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) 1951eb283dSJackson Donaldson 2051eb283dSJackson Donaldson #define FLASH_BASE_ADDRESS 0x10000000 2151eb283dSJackson Donaldson #define FLASH_SIZE (512 * 1024) 2251eb283dSJackson Donaldson #define SRAM_BASE_ADDRESS 0x20000000 2351eb283dSJackson Donaldson #define SRAM_SIZE (128 * 1024) 2451eb283dSJackson Donaldson 25*65714d3eSJackson Donaldson /* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */ 26*65714d3eSJackson Donaldson #define MAX78000_NUM_ICC 2 27*65714d3eSJackson Donaldson 2851eb283dSJackson Donaldson struct MAX78000State { 2951eb283dSJackson Donaldson SysBusDevice parent_obj; 3051eb283dSJackson Donaldson 3151eb283dSJackson Donaldson ARMv7MState armv7m; 3251eb283dSJackson Donaldson 3351eb283dSJackson Donaldson MemoryRegion sram; 3451eb283dSJackson Donaldson MemoryRegion flash; 3551eb283dSJackson Donaldson 36*65714d3eSJackson Donaldson Max78000IccState icc[MAX78000_NUM_ICC]; 37*65714d3eSJackson Donaldson 3851eb283dSJackson Donaldson Clock *sysclk; 3951eb283dSJackson Donaldson }; 4051eb283dSJackson Donaldson 4151eb283dSJackson Donaldson #endif 42