xref: /openbmc/qemu/include/hw/arm/fsl-imx8mp.h (revision a4eefc69b23713c4e5981d9d91a6e15dfd4496fe)
1 /*
2  * i.MX 8M Plus SoC Definitions
3  *
4  * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com>
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #ifndef FSL_IMX8MP_H
10 #define FSL_IMX8MP_H
11 
12 #include "cpu.h"
13 #include "hw/char/imx_serial.h"
14 #include "hw/intc/arm_gicv3_common.h"
15 #include "qom/object.h"
16 #include "qemu/units.h"
17 
18 #define TYPE_FSL_IMX8MP "fsl-imx8mp"
19 OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
20 
21 #define FSL_IMX8MP_RAM_START        0x40000000
22 #define FSL_IMX8MP_RAM_SIZE_MAX     (8 * GiB)
23 
24 enum FslImx8mpConfiguration {
25     FSL_IMX8MP_NUM_CPUS         = 4,
26     FSL_IMX8MP_NUM_IRQS         = 160,
27     FSL_IMX8MP_NUM_UARTS        = 4,
28 };
29 
30 struct FslImx8mpState {
31     DeviceState    parent_obj;
32 
33     ARMCPU             cpu[FSL_IMX8MP_NUM_CPUS];
34     GICv3State         gic;
35     IMXSerialState     uart[FSL_IMX8MP_NUM_UARTS];
36 };
37 
38 enum FslImx8mpMemoryRegions {
39     FSL_IMX8MP_A53_DAP,
40     FSL_IMX8MP_AIPS1_CONFIGURATION,
41     FSL_IMX8MP_AIPS2_CONFIGURATION,
42     FSL_IMX8MP_AIPS3_CONFIGURATION,
43     FSL_IMX8MP_AIPS4_CONFIGURATION,
44     FSL_IMX8MP_AIPS5_CONFIGURATION,
45     FSL_IMX8MP_ANA_OSC,
46     FSL_IMX8MP_ANA_PLL,
47     FSL_IMX8MP_ANA_TSENSOR,
48     FSL_IMX8MP_APBH_DMA,
49     FSL_IMX8MP_ASRC,
50     FSL_IMX8MP_AUDIO_BLK_CTRL,
51     FSL_IMX8MP_AUDIO_DSP,
52     FSL_IMX8MP_AUDIO_XCVR_RX,
53     FSL_IMX8MP_AUD_IRQ_STEER,
54     FSL_IMX8MP_BOOT_ROM,
55     FSL_IMX8MP_BOOT_ROM_PROTECTED,
56     FSL_IMX8MP_CAAM,
57     FSL_IMX8MP_CAAM_MEM,
58     FSL_IMX8MP_CCM,
59     FSL_IMX8MP_CSU,
60     FSL_IMX8MP_DDR_BLK_CTRL,
61     FSL_IMX8MP_DDR_CTL,
62     FSL_IMX8MP_DDR_PERF_MON,
63     FSL_IMX8MP_DDR_PHY,
64     FSL_IMX8MP_DDR_PHY_BROADCAST,
65     FSL_IMX8MP_ECSPI1,
66     FSL_IMX8MP_ECSPI2,
67     FSL_IMX8MP_ECSPI3,
68     FSL_IMX8MP_EDMA_CHANNELS,
69     FSL_IMX8MP_EDMA_MANAGEMENT_PAGE,
70     FSL_IMX8MP_ENET1,
71     FSL_IMX8MP_ENET2_TSN,
72     FSL_IMX8MP_FLEXCAN1,
73     FSL_IMX8MP_FLEXCAN2,
74     FSL_IMX8MP_GIC_DIST,
75     FSL_IMX8MP_GIC_REDIST,
76     FSL_IMX8MP_GPC,
77     FSL_IMX8MP_GPIO1,
78     FSL_IMX8MP_GPIO2,
79     FSL_IMX8MP_GPIO3,
80     FSL_IMX8MP_GPIO4,
81     FSL_IMX8MP_GPIO5,
82     FSL_IMX8MP_GPT1,
83     FSL_IMX8MP_GPT2,
84     FSL_IMX8MP_GPT3,
85     FSL_IMX8MP_GPT4,
86     FSL_IMX8MP_GPT5,
87     FSL_IMX8MP_GPT6,
88     FSL_IMX8MP_GPU2D,
89     FSL_IMX8MP_GPU3D,
90     FSL_IMX8MP_HDMI_TX,
91     FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR,
92     FSL_IMX8MP_HSIO_BLK_CTL,
93     FSL_IMX8MP_I2C1,
94     FSL_IMX8MP_I2C2,
95     FSL_IMX8MP_I2C3,
96     FSL_IMX8MP_I2C4,
97     FSL_IMX8MP_I2C5,
98     FSL_IMX8MP_I2C6,
99     FSL_IMX8MP_INTERCONNECT,
100     FSL_IMX8MP_IOMUXC,
101     FSL_IMX8MP_IOMUXC_GPR,
102     FSL_IMX8MP_IPS_DEWARP,
103     FSL_IMX8MP_ISI,
104     FSL_IMX8MP_ISP1,
105     FSL_IMX8MP_ISP2,
106     FSL_IMX8MP_LCDIF1,
107     FSL_IMX8MP_LCDIF2,
108     FSL_IMX8MP_MEDIA_BLK_CTL,
109     FSL_IMX8MP_MIPI_CSI1,
110     FSL_IMX8MP_MIPI_CSI2,
111     FSL_IMX8MP_MIPI_DSI1,
112     FSL_IMX8MP_MU_1_A,
113     FSL_IMX8MP_MU_1_B,
114     FSL_IMX8MP_MU_2_A,
115     FSL_IMX8MP_MU_2_B,
116     FSL_IMX8MP_MU_3_A,
117     FSL_IMX8MP_MU_3_B,
118     FSL_IMX8MP_NPU,
119     FSL_IMX8MP_OCOTP_CTRL,
120     FSL_IMX8MP_OCRAM,
121     FSL_IMX8MP_OCRAM_S,
122     FSL_IMX8MP_PCIE1,
123     FSL_IMX8MP_PCIE1_MEM,
124     FSL_IMX8MP_PCIE_PHY1,
125     FSL_IMX8MP_PDM,
126     FSL_IMX8MP_PERFMON1,
127     FSL_IMX8MP_PERFMON2,
128     FSL_IMX8MP_PWM1,
129     FSL_IMX8MP_PWM2,
130     FSL_IMX8MP_PWM3,
131     FSL_IMX8MP_PWM4,
132     FSL_IMX8MP_QOSC,
133     FSL_IMX8MP_QSPI,
134     FSL_IMX8MP_QSPI1_RX_BUFFER,
135     FSL_IMX8MP_QSPI1_TX_BUFFER,
136     FSL_IMX8MP_QSPI_MEM,
137     FSL_IMX8MP_RAM,
138     FSL_IMX8MP_RDC,
139     FSL_IMX8MP_SAI1,
140     FSL_IMX8MP_SAI2,
141     FSL_IMX8MP_SAI3,
142     FSL_IMX8MP_SAI5,
143     FSL_IMX8MP_SAI6,
144     FSL_IMX8MP_SAI7,
145     FSL_IMX8MP_SDMA1,
146     FSL_IMX8MP_SDMA2,
147     FSL_IMX8MP_SDMA3,
148     FSL_IMX8MP_SEMAPHORE1,
149     FSL_IMX8MP_SEMAPHORE2,
150     FSL_IMX8MP_SEMAPHORE_HS,
151     FSL_IMX8MP_SNVS_HP,
152     FSL_IMX8MP_SPBA1,
153     FSL_IMX8MP_SPBA2,
154     FSL_IMX8MP_SRC,
155     FSL_IMX8MP_SYSCNT_CMP,
156     FSL_IMX8MP_SYSCNT_CTRL,
157     FSL_IMX8MP_SYSCNT_RD,
158     FSL_IMX8MP_TCM_DTCM,
159     FSL_IMX8MP_TCM_ITCM,
160     FSL_IMX8MP_TZASC,
161     FSL_IMX8MP_UART1,
162     FSL_IMX8MP_UART2,
163     FSL_IMX8MP_UART3,
164     FSL_IMX8MP_UART4,
165     FSL_IMX8MP_USB1,
166     FSL_IMX8MP_USB2,
167     FSL_IMX8MP_USDHC1,
168     FSL_IMX8MP_USDHC2,
169     FSL_IMX8MP_USDHC3,
170     FSL_IMX8MP_VPU,
171     FSL_IMX8MP_VPU_BLK_CTRL,
172     FSL_IMX8MP_VPU_G1_DECODER,
173     FSL_IMX8MP_VPU_G2_DECODER,
174     FSL_IMX8MP_VPU_VC8000E_ENCODER,
175     FSL_IMX8MP_WDOG1,
176     FSL_IMX8MP_WDOG2,
177     FSL_IMX8MP_WDOG3,
178 };
179 
180 enum FslImx8mpIrqs {
181     FSL_IMX8MP_UART1_IRQ    = 26,
182     FSL_IMX8MP_UART2_IRQ    = 27,
183     FSL_IMX8MP_UART3_IRQ    = 28,
184     FSL_IMX8MP_UART4_IRQ    = 29,
185     FSL_IMX8MP_UART5_IRQ    = 30,
186     FSL_IMX8MP_UART6_IRQ    = 16,
187 };
188 
189 #endif /* FSL_IMX8MP_H */
190