1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef FSL_IMX7_H 20 #define FSL_IMX7_H 21 22 #include "hw/arm/boot.h" 23 #include "hw/cpu/a15mpcore.h" 24 #include "hw/intc/imx_gpcv2.h" 25 #include "hw/misc/imx7_ccm.h" 26 #include "hw/misc/imx7_snvs.h" 27 #include "hw/misc/imx7_gpr.h" 28 #include "hw/misc/imx7_src.h" 29 #include "hw/watchdog/wdt_imx2.h" 30 #include "hw/gpio/imx_gpio.h" 31 #include "hw/char/imx_serial.h" 32 #include "hw/timer/imx_gpt.h" 33 #include "hw/timer/imx_epit.h" 34 #include "hw/i2c/imx_i2c.h" 35 #include "hw/sd/sdhci.h" 36 #include "hw/ssi/imx_spi.h" 37 #include "hw/net/imx_fec.h" 38 #include "hw/pci-host/designware.h" 39 #include "hw/usb/chipidea.h" 40 #include "cpu.h" 41 #include "qom/object.h" 42 #include "qemu/units.h" 43 44 #define TYPE_FSL_IMX7 "fsl-imx7" 45 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) 46 47 enum FslIMX7Configuration { 48 FSL_IMX7_NUM_CPUS = 2, 49 FSL_IMX7_NUM_UARTS = 7, 50 FSL_IMX7_NUM_ETHS = 2, 51 FSL_IMX7_ETH_NUM_TX_RINGS = 3, 52 FSL_IMX7_NUM_USDHCS = 3, 53 FSL_IMX7_NUM_WDTS = 4, 54 FSL_IMX7_NUM_GPTS = 4, 55 FSL_IMX7_NUM_IOMUXCS = 2, 56 FSL_IMX7_NUM_GPIOS = 7, 57 FSL_IMX7_NUM_I2CS = 4, 58 FSL_IMX7_NUM_ECSPIS = 4, 59 FSL_IMX7_NUM_USBS = 3, 60 FSL_IMX7_NUM_ADCS = 2, 61 FSL_IMX7_NUM_SAIS = 3, 62 FSL_IMX7_NUM_CANS = 2, 63 FSL_IMX7_NUM_PWMS = 4, 64 }; 65 66 struct FslIMX7State { 67 /*< private >*/ 68 DeviceState parent_obj; 69 70 /*< public >*/ 71 ARMCPU cpu[FSL_IMX7_NUM_CPUS]; 72 A15MPPrivState a7mpcore; 73 IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; 74 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; 75 IMX7CCMState ccm; 76 IMX7AnalogState analog; 77 IMX7SNVSState snvs; 78 IMX7SRCState src; 79 IMXGPCv2State gpcv2; 80 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; 81 IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; 82 IMXSerialState uart[FSL_IMX7_NUM_UARTS]; 83 IMXFECState eth[FSL_IMX7_NUM_ETHS]; 84 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; 85 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; 86 IMX7GPRState gpr; 87 ChipideaState usb[FSL_IMX7_NUM_USBS]; 88 DesignwarePCIEHost pcie; 89 MemoryRegion rom; 90 MemoryRegion caam; 91 MemoryRegion ocram; 92 MemoryRegion ocram_epdc; 93 MemoryRegion ocram_pxp; 94 MemoryRegion ocram_s; 95 96 uint32_t phy_num[FSL_IMX7_NUM_ETHS]; 97 bool phy_connected[FSL_IMX7_NUM_ETHS]; 98 }; 99 100 enum FslIMX7MemoryMap { 101 FSL_IMX7_MMDC_ADDR = 0x80000000, 102 FSL_IMX7_MMDC_SIZE = (2 * GiB), 103 104 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, 105 FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), 106 107 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, 108 FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), 109 110 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, 111 FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), 112 113 /* PCIe Peripherals */ 114 FSL_IMX7_PCIE_REG_ADDR = 0x33800000, 115 116 /* MMAP Peripherals */ 117 FSL_IMX7_DMA_APBH_ADDR = 0x33000000, 118 FSL_IMX7_DMA_APBH_SIZE = 0x8000, 119 120 /* GPV configuration */ 121 FSL_IMX7_GPV6_ADDR = 0x32600000, 122 FSL_IMX7_GPV5_ADDR = 0x32500000, 123 FSL_IMX7_GPV4_ADDR = 0x32400000, 124 FSL_IMX7_GPV3_ADDR = 0x32300000, 125 FSL_IMX7_GPV2_ADDR = 0x32200000, 126 FSL_IMX7_GPV1_ADDR = 0x32100000, 127 FSL_IMX7_GPV0_ADDR = 0x32000000, 128 FSL_IMX7_GPVn_SIZE = (1 * MiB), 129 130 /* Arm Peripherals */ 131 FSL_IMX7_A7MPCORE_ADDR = 0x31000000, 132 133 /* AIPS-3 Begin */ 134 135 FSL_IMX7_ENET2_ADDR = 0x30BF0000, 136 FSL_IMX7_ENET1_ADDR = 0x30BE0000, 137 138 FSL_IMX7_SDMA_ADDR = 0x30BD0000, 139 FSL_IMX7_SDMA_SIZE = (4 * KiB), 140 141 FSL_IMX7_EIM_ADDR = 0x30BC0000, 142 FSL_IMX7_EIM_SIZE = (4 * KiB), 143 144 FSL_IMX7_QSPI_ADDR = 0x30BB0000, 145 FSL_IMX7_QSPI_SIZE = 0x8000, 146 147 FSL_IMX7_SIM2_ADDR = 0x30BA0000, 148 FSL_IMX7_SIM1_ADDR = 0x30B90000, 149 FSL_IMX7_SIMn_SIZE = (4 * KiB), 150 151 FSL_IMX7_USDHC3_ADDR = 0x30B60000, 152 FSL_IMX7_USDHC2_ADDR = 0x30B50000, 153 FSL_IMX7_USDHC1_ADDR = 0x30B40000, 154 155 FSL_IMX7_USB3_ADDR = 0x30B30000, 156 FSL_IMX7_USBMISC3_ADDR = 0x30B30200, 157 FSL_IMX7_USB2_ADDR = 0x30B20000, 158 FSL_IMX7_USBMISC2_ADDR = 0x30B20200, 159 FSL_IMX7_USB1_ADDR = 0x30B10000, 160 FSL_IMX7_USBMISC1_ADDR = 0x30B10200, 161 FSL_IMX7_USBMISCn_SIZE = 0x200, 162 163 FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, 164 FSL_IMX7_USB_PL301_SIZE = (64 * KiB), 165 166 FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, 167 FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), 168 169 FSL_IMX7_MUB_ADDR = 0x30AB0000, 170 FSL_IMX7_MUA_ADDR = 0x30AA0000, 171 FSL_IMX7_MUn_SIZE = (KiB), 172 173 FSL_IMX7_UART7_ADDR = 0x30A90000, 174 FSL_IMX7_UART6_ADDR = 0x30A80000, 175 FSL_IMX7_UART5_ADDR = 0x30A70000, 176 FSL_IMX7_UART4_ADDR = 0x30A60000, 177 178 FSL_IMX7_I2C4_ADDR = 0x30A50000, 179 FSL_IMX7_I2C3_ADDR = 0x30A40000, 180 FSL_IMX7_I2C2_ADDR = 0x30A30000, 181 FSL_IMX7_I2C1_ADDR = 0x30A20000, 182 183 FSL_IMX7_CAN2_ADDR = 0x30A10000, 184 FSL_IMX7_CAN1_ADDR = 0x30A00000, 185 FSL_IMX7_CANn_SIZE = (4 * KiB), 186 187 FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, 188 FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), 189 190 FSL_IMX7_CAAM_ADDR = 0x30900000, 191 FSL_IMX7_CAAM_SIZE = (256 * KiB), 192 193 FSL_IMX7_SPBA_ADDR = 0x308F0000, 194 FSL_IMX7_SPBA_SIZE = (4 * KiB), 195 196 FSL_IMX7_SAI3_ADDR = 0x308C0000, 197 FSL_IMX7_SAI2_ADDR = 0x308B0000, 198 FSL_IMX7_SAI1_ADDR = 0x308A0000, 199 FSL_IMX7_SAIn_SIZE = (4 * KiB), 200 201 FSL_IMX7_UART3_ADDR = 0x30880000, 202 /* 203 * Some versions of the reference manual claim that UART2 is @ 204 * 0x30870000, but experiments with HW + DT files in upstream 205 * Linux kernel show that not to be true and that block is 206 * actually located @ 0x30890000 207 */ 208 FSL_IMX7_UART2_ADDR = 0x30890000, 209 FSL_IMX7_UART1_ADDR = 0x30860000, 210 211 FSL_IMX7_ECSPI3_ADDR = 0x30840000, 212 FSL_IMX7_ECSPI2_ADDR = 0x30830000, 213 FSL_IMX7_ECSPI1_ADDR = 0x30820000, 214 FSL_IMX7_ECSPIn_SIZE = (4 * KiB), 215 216 /* AIPS-3 End */ 217 218 /* AIPS-2 Begin */ 219 220 FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, 221 FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), 222 223 FSL_IMX7_PERFMON2_ADDR = 0x307D0000, 224 FSL_IMX7_PERFMON1_ADDR = 0x307C0000, 225 FSL_IMX7_PERFMONn_SIZE = (64 * KiB), 226 227 FSL_IMX7_DDRC_ADDR = 0x307A0000, 228 FSL_IMX7_DDRC_SIZE = (4 * KiB), 229 230 FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, 231 FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), 232 233 FSL_IMX7_TZASC_ADDR = 0x30780000, 234 FSL_IMX7_TZASC_SIZE = (64 * KiB), 235 236 FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, 237 FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), 238 239 FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, 240 FSL_IMX7_MIPI_CSI_SIZE = 0x4000, 241 242 FSL_IMX7_LCDIF_ADDR = 0x30730000, 243 FSL_IMX7_LCDIF_SIZE = 0x8000, 244 245 FSL_IMX7_CSI_ADDR = 0x30710000, 246 FSL_IMX7_CSI_SIZE = (4 * KiB), 247 248 FSL_IMX7_PXP_ADDR = 0x30700000, 249 FSL_IMX7_PXP_SIZE = 0x4000, 250 251 FSL_IMX7_EPDC_ADDR = 0x306F0000, 252 FSL_IMX7_EPDC_SIZE = (4 * KiB), 253 254 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, 255 FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), 256 257 FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, 258 FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, 259 FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, 260 261 FSL_IMX7_PWM4_ADDR = 0x30690000, 262 FSL_IMX7_PWM3_ADDR = 0x30680000, 263 FSL_IMX7_PWM2_ADDR = 0x30670000, 264 FSL_IMX7_PWM1_ADDR = 0x30660000, 265 FSL_IMX7_PWMn_SIZE = (4 * KiB), 266 267 FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, 268 FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, 269 FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), 270 271 FSL_IMX7_ECSPI4_ADDR = 0x30630000, 272 273 FSL_IMX7_ADC2_ADDR = 0x30620000, 274 FSL_IMX7_ADC1_ADDR = 0x30610000, 275 FSL_IMX7_ADCn_SIZE = (4 * KiB), 276 277 FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, 278 FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), 279 280 /* AIPS-2 End */ 281 282 /* AIPS-1 Begin */ 283 284 FSL_IMX7_CSU_ADDR = 0x303E0000, 285 FSL_IMX7_CSU_SIZE = (64 * KiB), 286 287 FSL_IMX7_RDC_ADDR = 0x303D0000, 288 FSL_IMX7_RDC_SIZE = (4 * KiB), 289 290 FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, 291 FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, 292 FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), 293 294 FSL_IMX7_GPC_ADDR = 0x303A0000, 295 296 FSL_IMX7_SRC_ADDR = 0x30390000, 297 298 FSL_IMX7_CCM_ADDR = 0x30380000, 299 300 FSL_IMX7_SNVS_HP_ADDR = 0x30370000, 301 302 FSL_IMX7_ANALOG_ADDR = 0x30360000, 303 304 FSL_IMX7_OCOTP_ADDR = 0x30350000, 305 FSL_IMX7_OCOTP_SIZE = 0x10000, 306 307 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, 308 FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), 309 310 FSL_IMX7_IOMUXC_ADDR = 0x30330000, 311 FSL_IMX7_IOMUXC_SIZE = (4 * KiB), 312 313 FSL_IMX7_KPP_ADDR = 0x30320000, 314 FSL_IMX7_KPP_SIZE = (4 * KiB), 315 316 FSL_IMX7_ROMCP_ADDR = 0x30310000, 317 FSL_IMX7_ROMCP_SIZE = (4 * KiB), 318 319 FSL_IMX7_GPT4_ADDR = 0x30300000, 320 FSL_IMX7_GPT3_ADDR = 0x302F0000, 321 FSL_IMX7_GPT2_ADDR = 0x302E0000, 322 FSL_IMX7_GPT1_ADDR = 0x302D0000, 323 324 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, 325 FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), 326 327 FSL_IMX7_WDOG4_ADDR = 0x302B0000, 328 FSL_IMX7_WDOG3_ADDR = 0x302A0000, 329 FSL_IMX7_WDOG2_ADDR = 0x30290000, 330 FSL_IMX7_WDOG1_ADDR = 0x30280000, 331 332 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, 333 334 FSL_IMX7_GPIO7_ADDR = 0x30260000, 335 FSL_IMX7_GPIO6_ADDR = 0x30250000, 336 FSL_IMX7_GPIO5_ADDR = 0x30240000, 337 FSL_IMX7_GPIO4_ADDR = 0x30230000, 338 FSL_IMX7_GPIO3_ADDR = 0x30220000, 339 FSL_IMX7_GPIO2_ADDR = 0x30210000, 340 FSL_IMX7_GPIO1_ADDR = 0x30200000, 341 342 FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, 343 FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), 344 345 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, 346 FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), 347 348 /* AIPS-1 End */ 349 350 FSL_IMX7_EIM_CS0_ADDR = 0x28000000, 351 FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), 352 353 FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, 354 FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), 355 356 FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, 357 FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), 358 359 FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, 360 FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), 361 362 FSL_IMX7_TCMU_ADDR = 0x00800000, 363 FSL_IMX7_TCMU_SIZE = (32 * KiB), 364 365 FSL_IMX7_TCML_ADDR = 0x007F8000, 366 FSL_IMX7_TCML_SIZE = (32 * KiB), 367 368 FSL_IMX7_OCRAM_S_ADDR = 0x00180000, 369 FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), 370 371 FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, 372 FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), 373 374 FSL_IMX7_ROM_ADDR = 0x00000000, 375 FSL_IMX7_ROM_SIZE = (96 * KiB), 376 }; 377 378 enum FslIMX7IRQs { 379 FSL_IMX7_USDHC1_IRQ = 22, 380 FSL_IMX7_USDHC2_IRQ = 23, 381 FSL_IMX7_USDHC3_IRQ = 24, 382 383 FSL_IMX7_UART1_IRQ = 26, 384 FSL_IMX7_UART2_IRQ = 27, 385 FSL_IMX7_UART3_IRQ = 28, 386 FSL_IMX7_UART4_IRQ = 29, 387 FSL_IMX7_UART5_IRQ = 30, 388 FSL_IMX7_UART6_IRQ = 16, 389 390 FSL_IMX7_ECSPI1_IRQ = 31, 391 FSL_IMX7_ECSPI2_IRQ = 32, 392 FSL_IMX7_ECSPI3_IRQ = 33, 393 FSL_IMX7_ECSPI4_IRQ = 34, 394 395 FSL_IMX7_I2C1_IRQ = 35, 396 FSL_IMX7_I2C2_IRQ = 36, 397 FSL_IMX7_I2C3_IRQ = 37, 398 FSL_IMX7_I2C4_IRQ = 38, 399 400 FSL_IMX7_USB1_IRQ = 43, 401 FSL_IMX7_USB2_IRQ = 42, 402 FSL_IMX7_USB3_IRQ = 40, 403 404 FSL_IMX7_GPT1_IRQ = 55, 405 FSL_IMX7_GPT2_IRQ = 54, 406 FSL_IMX7_GPT3_IRQ = 53, 407 FSL_IMX7_GPT4_IRQ = 52, 408 409 FSL_IMX7_GPIO1_LOW_IRQ = 64, 410 FSL_IMX7_GPIO1_HIGH_IRQ = 65, 411 FSL_IMX7_GPIO2_LOW_IRQ = 66, 412 FSL_IMX7_GPIO2_HIGH_IRQ = 67, 413 FSL_IMX7_GPIO3_LOW_IRQ = 68, 414 FSL_IMX7_GPIO3_HIGH_IRQ = 69, 415 FSL_IMX7_GPIO4_LOW_IRQ = 70, 416 FSL_IMX7_GPIO4_HIGH_IRQ = 71, 417 FSL_IMX7_GPIO5_LOW_IRQ = 72, 418 FSL_IMX7_GPIO5_HIGH_IRQ = 73, 419 FSL_IMX7_GPIO6_LOW_IRQ = 74, 420 FSL_IMX7_GPIO6_HIGH_IRQ = 75, 421 FSL_IMX7_GPIO7_LOW_IRQ = 76, 422 FSL_IMX7_GPIO7_HIGH_IRQ = 77, 423 424 FSL_IMX7_WDOG1_IRQ = 78, 425 FSL_IMX7_WDOG2_IRQ = 79, 426 FSL_IMX7_WDOG3_IRQ = 10, 427 FSL_IMX7_WDOG4_IRQ = 109, 428 429 FSL_IMX7_PCI_INTA_IRQ = 125, 430 FSL_IMX7_PCI_INTB_IRQ = 124, 431 FSL_IMX7_PCI_INTC_IRQ = 123, 432 FSL_IMX7_PCI_INTD_IRQ = 122, 433 434 FSL_IMX7_UART7_IRQ = 126, 435 436 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) 437 438 FSL_IMX7_MAX_IRQ = 128, 439 }; 440 441 #endif /* FSL_IMX7_H */ 442