1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef FSL_IMX7_H 20 #define FSL_IMX7_H 21 22 #include "hw/arm/arm.h" 23 #include "hw/cpu/a15mpcore.h" 24 #include "hw/intc/imx_gpcv2.h" 25 #include "hw/misc/imx7_ccm.h" 26 #include "hw/misc/imx7_snvs.h" 27 #include "hw/misc/imx7_gpr.h" 28 #include "hw/misc/imx6_src.h" 29 #include "hw/misc/imx2_wdt.h" 30 #include "hw/gpio/imx_gpio.h" 31 #include "hw/char/imx_serial.h" 32 #include "hw/timer/imx_gpt.h" 33 #include "hw/timer/imx_epit.h" 34 #include "hw/i2c/imx_i2c.h" 35 #include "hw/gpio/imx_gpio.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/ssi/imx_spi.h" 38 #include "hw/net/imx_fec.h" 39 #include "hw/pci-host/designware.h" 40 #include "hw/usb/chipidea.h" 41 #include "exec/memory.h" 42 #include "cpu.h" 43 44 #define TYPE_FSL_IMX7 "fsl,imx7" 45 #define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7) 46 47 enum FslIMX7Configuration { 48 FSL_IMX7_NUM_CPUS = 2, 49 FSL_IMX7_NUM_UARTS = 7, 50 FSL_IMX7_NUM_ETHS = 2, 51 FSL_IMX7_ETH_NUM_TX_RINGS = 3, 52 FSL_IMX7_NUM_USDHCS = 3, 53 FSL_IMX7_NUM_WDTS = 4, 54 FSL_IMX7_NUM_GPTS = 4, 55 FSL_IMX7_NUM_IOMUXCS = 2, 56 FSL_IMX7_NUM_GPIOS = 7, 57 FSL_IMX7_NUM_I2CS = 4, 58 FSL_IMX7_NUM_ECSPIS = 4, 59 FSL_IMX7_NUM_USBS = 3, 60 FSL_IMX7_NUM_ADCS = 2, 61 }; 62 63 typedef struct FslIMX7State { 64 /*< private >*/ 65 DeviceState parent_obj; 66 67 /*< public >*/ 68 ARMCPU cpu[FSL_IMX7_NUM_CPUS]; 69 A15MPPrivState a7mpcore; 70 IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; 71 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; 72 IMX7CCMState ccm; 73 IMX7AnalogState analog; 74 IMX7SNVSState snvs; 75 IMXGPCv2State gpcv2; 76 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; 77 IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; 78 IMXSerialState uart[FSL_IMX7_NUM_UARTS]; 79 IMXFECState eth[FSL_IMX7_NUM_ETHS]; 80 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; 81 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; 82 IMX7GPRState gpr; 83 ChipideaState usb[FSL_IMX7_NUM_USBS]; 84 DesignwarePCIEHost pcie; 85 } FslIMX7State; 86 87 enum FslIMX7MemoryMap { 88 FSL_IMX7_MMDC_ADDR = 0x80000000, 89 FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, 90 91 FSL_IMX7_GPIO1_ADDR = 0x30200000, 92 FSL_IMX7_GPIO2_ADDR = 0x30210000, 93 FSL_IMX7_GPIO3_ADDR = 0x30220000, 94 FSL_IMX7_GPIO4_ADDR = 0x30230000, 95 FSL_IMX7_GPIO5_ADDR = 0x30240000, 96 FSL_IMX7_GPIO6_ADDR = 0x30250000, 97 FSL_IMX7_GPIO7_ADDR = 0x30260000, 98 99 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, 100 101 FSL_IMX7_WDOG1_ADDR = 0x30280000, 102 FSL_IMX7_WDOG2_ADDR = 0x30290000, 103 FSL_IMX7_WDOG3_ADDR = 0x302A0000, 104 FSL_IMX7_WDOG4_ADDR = 0x302B0000, 105 106 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, 107 108 FSL_IMX7_GPT1_ADDR = 0x302D0000, 109 FSL_IMX7_GPT2_ADDR = 0x302E0000, 110 FSL_IMX7_GPT3_ADDR = 0x302F0000, 111 FSL_IMX7_GPT4_ADDR = 0x30300000, 112 113 FSL_IMX7_IOMUXC_ADDR = 0x30330000, 114 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, 115 FSL_IMX7_IOMUXCn_SIZE = 0x1000, 116 117 FSL_IMX7_ANALOG_ADDR = 0x30360000, 118 FSL_IMX7_SNVS_ADDR = 0x30370000, 119 FSL_IMX7_CCM_ADDR = 0x30380000, 120 121 FSL_IMX7_SRC_ADDR = 0x30390000, 122 FSL_IMX7_SRC_SIZE = 0x1000, 123 124 FSL_IMX7_ADC1_ADDR = 0x30610000, 125 FSL_IMX7_ADC2_ADDR = 0x30620000, 126 FSL_IMX7_ADCn_SIZE = 0x1000, 127 128 FSL_IMX7_GPC_ADDR = 0x303A0000, 129 130 FSL_IMX7_I2C1_ADDR = 0x30A20000, 131 FSL_IMX7_I2C2_ADDR = 0x30A30000, 132 FSL_IMX7_I2C3_ADDR = 0x30A40000, 133 FSL_IMX7_I2C4_ADDR = 0x30A50000, 134 135 FSL_IMX7_ECSPI1_ADDR = 0x30820000, 136 FSL_IMX7_ECSPI2_ADDR = 0x30830000, 137 FSL_IMX7_ECSPI3_ADDR = 0x30840000, 138 FSL_IMX7_ECSPI4_ADDR = 0x30630000, 139 140 FSL_IMX7_LCDIF_ADDR = 0x30730000, 141 FSL_IMX7_LCDIF_SIZE = 0x1000, 142 143 FSL_IMX7_UART1_ADDR = 0x30860000, 144 /* 145 * Some versions of the reference manual claim that UART2 is @ 146 * 0x30870000, but experiments with HW + DT files in upstream 147 * Linux kernel show that not to be true and that block is 148 * acutally located @ 0x30890000 149 */ 150 FSL_IMX7_UART2_ADDR = 0x30890000, 151 FSL_IMX7_UART3_ADDR = 0x30880000, 152 FSL_IMX7_UART4_ADDR = 0x30A60000, 153 FSL_IMX7_UART5_ADDR = 0x30A70000, 154 FSL_IMX7_UART6_ADDR = 0x30A80000, 155 FSL_IMX7_UART7_ADDR = 0x30A90000, 156 157 FSL_IMX7_ENET1_ADDR = 0x30BE0000, 158 FSL_IMX7_ENET2_ADDR = 0x30BF0000, 159 160 FSL_IMX7_USB1_ADDR = 0x30B10000, 161 FSL_IMX7_USBMISC1_ADDR = 0x30B10200, 162 FSL_IMX7_USB2_ADDR = 0x30B20000, 163 FSL_IMX7_USBMISC2_ADDR = 0x30B20200, 164 FSL_IMX7_USB3_ADDR = 0x30B30000, 165 FSL_IMX7_USBMISC3_ADDR = 0x30B30200, 166 FSL_IMX7_USBMISCn_SIZE = 0x200, 167 168 FSL_IMX7_USDHC1_ADDR = 0x30B40000, 169 FSL_IMX7_USDHC2_ADDR = 0x30B50000, 170 FSL_IMX7_USDHC3_ADDR = 0x30B60000, 171 172 FSL_IMX7_SDMA_ADDR = 0x30BD0000, 173 FSL_IMX7_SDMA_SIZE = 0x1000, 174 175 FSL_IMX7_A7MPCORE_ADDR = 0x31000000, 176 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, 177 178 FSL_IMX7_PCIE_REG_ADDR = 0x33800000, 179 FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, 180 181 FSL_IMX7_GPR_ADDR = 0x30340000, 182 }; 183 184 enum FslIMX7IRQs { 185 FSL_IMX7_USDHC1_IRQ = 22, 186 FSL_IMX7_USDHC2_IRQ = 23, 187 FSL_IMX7_USDHC3_IRQ = 24, 188 189 FSL_IMX7_UART1_IRQ = 26, 190 FSL_IMX7_UART2_IRQ = 27, 191 FSL_IMX7_UART3_IRQ = 28, 192 FSL_IMX7_UART4_IRQ = 29, 193 FSL_IMX7_UART5_IRQ = 30, 194 FSL_IMX7_UART6_IRQ = 16, 195 196 FSL_IMX7_ECSPI1_IRQ = 31, 197 FSL_IMX7_ECSPI2_IRQ = 32, 198 FSL_IMX7_ECSPI3_IRQ = 33, 199 FSL_IMX7_ECSPI4_IRQ = 34, 200 201 FSL_IMX7_I2C1_IRQ = 35, 202 FSL_IMX7_I2C2_IRQ = 36, 203 FSL_IMX7_I2C3_IRQ = 37, 204 FSL_IMX7_I2C4_IRQ = 38, 205 206 FSL_IMX7_USB1_IRQ = 43, 207 FSL_IMX7_USB2_IRQ = 42, 208 FSL_IMX7_USB3_IRQ = 40, 209 210 FSL_IMX7_PCI_INTA_IRQ = 122, 211 FSL_IMX7_PCI_INTB_IRQ = 123, 212 FSL_IMX7_PCI_INTC_IRQ = 124, 213 FSL_IMX7_PCI_INTD_IRQ = 125, 214 215 FSL_IMX7_UART7_IRQ = 126, 216 217 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) 218 219 FSL_IMX7_MAX_IRQ = 128, 220 }; 221 222 #endif /* FSL_IMX7_H */ 223