1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef FSL_IMX7_H 20 #define FSL_IMX7_H 21 22 #include "hw/cpu/a15mpcore.h" 23 #include "hw/intc/imx_gpcv2.h" 24 #include "hw/misc/imx7_ccm.h" 25 #include "hw/misc/imx7_snvs.h" 26 #include "hw/misc/imx7_gpr.h" 27 #include "hw/misc/imx7_src.h" 28 #include "hw/watchdog/wdt_imx2.h" 29 #include "hw/gpio/imx_gpio.h" 30 #include "hw/char/imx_serial.h" 31 #include "hw/timer/imx_gpt.h" 32 #include "hw/timer/imx_epit.h" 33 #include "hw/i2c/imx_i2c.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/ssi/imx_spi.h" 36 #include "hw/net/imx_fec.h" 37 #include "hw/pci-host/designware.h" 38 #include "hw/usb/chipidea.h" 39 #include "cpu.h" 40 #include "qom/object.h" 41 #include "qemu/units.h" 42 43 #define TYPE_FSL_IMX7 "fsl-imx7" 44 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) 45 46 enum FslIMX7Configuration { 47 FSL_IMX7_NUM_CPUS = 2, 48 FSL_IMX7_NUM_UARTS = 7, 49 FSL_IMX7_NUM_ETHS = 2, 50 FSL_IMX7_ETH_NUM_TX_RINGS = 3, 51 FSL_IMX7_NUM_USDHCS = 3, 52 FSL_IMX7_NUM_WDTS = 4, 53 FSL_IMX7_NUM_GPTS = 4, 54 FSL_IMX7_NUM_IOMUXCS = 2, 55 FSL_IMX7_NUM_GPIOS = 7, 56 FSL_IMX7_NUM_I2CS = 4, 57 FSL_IMX7_NUM_ECSPIS = 4, 58 FSL_IMX7_NUM_USBS = 3, 59 FSL_IMX7_NUM_ADCS = 2, 60 FSL_IMX7_NUM_SAIS = 3, 61 FSL_IMX7_NUM_CANS = 2, 62 FSL_IMX7_NUM_PWMS = 4, 63 }; 64 65 struct FslIMX7State { 66 /*< private >*/ 67 DeviceState parent_obj; 68 69 /*< public >*/ 70 ARMCPU cpu[FSL_IMX7_NUM_CPUS]; 71 A15MPPrivState a7mpcore; 72 IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; 73 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; 74 IMX7CCMState ccm; 75 IMX7AnalogState analog; 76 IMX7SNVSState snvs; 77 IMX7SRCState src; 78 IMXGPCv2State gpcv2; 79 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; 80 IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; 81 IMXSerialState uart[FSL_IMX7_NUM_UARTS]; 82 IMXFECState eth[FSL_IMX7_NUM_ETHS]; 83 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; 84 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; 85 IMX7GPRState gpr; 86 ChipideaState usb[FSL_IMX7_NUM_USBS]; 87 DesignwarePCIEHost pcie; 88 MemoryRegion rom; 89 MemoryRegion caam; 90 MemoryRegion ocram; 91 MemoryRegion ocram_epdc; 92 MemoryRegion ocram_pxp; 93 MemoryRegion ocram_s; 94 95 uint32_t phy_num[FSL_IMX7_NUM_ETHS]; 96 bool phy_connected[FSL_IMX7_NUM_ETHS]; 97 }; 98 99 enum FslIMX7MemoryMap { 100 FSL_IMX7_MMDC_ADDR = 0x80000000, 101 FSL_IMX7_MMDC_SIZE = (2 * GiB), 102 103 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, 104 FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), 105 106 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, 107 FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), 108 109 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, 110 FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), 111 112 /* PCIe Peripherals */ 113 FSL_IMX7_PCIE_REG_ADDR = 0x33800000, 114 115 /* MMAP Peripherals */ 116 FSL_IMX7_DMA_APBH_ADDR = 0x33000000, 117 FSL_IMX7_DMA_APBH_SIZE = 0x8000, 118 119 /* GPV configuration */ 120 FSL_IMX7_GPV6_ADDR = 0x32600000, 121 FSL_IMX7_GPV5_ADDR = 0x32500000, 122 FSL_IMX7_GPV4_ADDR = 0x32400000, 123 FSL_IMX7_GPV3_ADDR = 0x32300000, 124 FSL_IMX7_GPV2_ADDR = 0x32200000, 125 FSL_IMX7_GPV1_ADDR = 0x32100000, 126 FSL_IMX7_GPV0_ADDR = 0x32000000, 127 FSL_IMX7_GPVn_SIZE = (1 * MiB), 128 129 /* Arm Peripherals */ 130 FSL_IMX7_A7MPCORE_ADDR = 0x31000000, 131 132 /* AIPS-3 Begin */ 133 134 FSL_IMX7_ENET2_ADDR = 0x30BF0000, 135 FSL_IMX7_ENET1_ADDR = 0x30BE0000, 136 137 FSL_IMX7_SDMA_ADDR = 0x30BD0000, 138 FSL_IMX7_SDMA_SIZE = (4 * KiB), 139 140 FSL_IMX7_EIM_ADDR = 0x30BC0000, 141 FSL_IMX7_EIM_SIZE = (4 * KiB), 142 143 FSL_IMX7_QSPI_ADDR = 0x30BB0000, 144 FSL_IMX7_QSPI_SIZE = 0x8000, 145 146 FSL_IMX7_SIM2_ADDR = 0x30BA0000, 147 FSL_IMX7_SIM1_ADDR = 0x30B90000, 148 FSL_IMX7_SIMn_SIZE = (4 * KiB), 149 150 FSL_IMX7_USDHC3_ADDR = 0x30B60000, 151 FSL_IMX7_USDHC2_ADDR = 0x30B50000, 152 FSL_IMX7_USDHC1_ADDR = 0x30B40000, 153 154 FSL_IMX7_USB3_ADDR = 0x30B30000, 155 FSL_IMX7_USBMISC3_ADDR = 0x30B30200, 156 FSL_IMX7_USB2_ADDR = 0x30B20000, 157 FSL_IMX7_USBMISC2_ADDR = 0x30B20200, 158 FSL_IMX7_USB1_ADDR = 0x30B10000, 159 FSL_IMX7_USBMISC1_ADDR = 0x30B10200, 160 FSL_IMX7_USBMISCn_SIZE = 0x200, 161 162 FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, 163 FSL_IMX7_USB_PL301_SIZE = (64 * KiB), 164 165 FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, 166 FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), 167 168 FSL_IMX7_MUB_ADDR = 0x30AB0000, 169 FSL_IMX7_MUA_ADDR = 0x30AA0000, 170 FSL_IMX7_MUn_SIZE = (KiB), 171 172 FSL_IMX7_UART7_ADDR = 0x30A90000, 173 FSL_IMX7_UART6_ADDR = 0x30A80000, 174 FSL_IMX7_UART5_ADDR = 0x30A70000, 175 FSL_IMX7_UART4_ADDR = 0x30A60000, 176 177 FSL_IMX7_I2C4_ADDR = 0x30A50000, 178 FSL_IMX7_I2C3_ADDR = 0x30A40000, 179 FSL_IMX7_I2C2_ADDR = 0x30A30000, 180 FSL_IMX7_I2C1_ADDR = 0x30A20000, 181 182 FSL_IMX7_CAN2_ADDR = 0x30A10000, 183 FSL_IMX7_CAN1_ADDR = 0x30A00000, 184 FSL_IMX7_CANn_SIZE = (4 * KiB), 185 186 FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, 187 FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), 188 189 FSL_IMX7_CAAM_ADDR = 0x30900000, 190 FSL_IMX7_CAAM_SIZE = (256 * KiB), 191 192 FSL_IMX7_SPBA_ADDR = 0x308F0000, 193 FSL_IMX7_SPBA_SIZE = (4 * KiB), 194 195 FSL_IMX7_SAI3_ADDR = 0x308C0000, 196 FSL_IMX7_SAI2_ADDR = 0x308B0000, 197 FSL_IMX7_SAI1_ADDR = 0x308A0000, 198 FSL_IMX7_SAIn_SIZE = (4 * KiB), 199 200 FSL_IMX7_UART3_ADDR = 0x30880000, 201 /* 202 * Some versions of the reference manual claim that UART2 is @ 203 * 0x30870000, but experiments with HW + DT files in upstream 204 * Linux kernel show that not to be true and that block is 205 * actually located @ 0x30890000 206 */ 207 FSL_IMX7_UART2_ADDR = 0x30890000, 208 FSL_IMX7_UART1_ADDR = 0x30860000, 209 210 FSL_IMX7_ECSPI3_ADDR = 0x30840000, 211 FSL_IMX7_ECSPI2_ADDR = 0x30830000, 212 FSL_IMX7_ECSPI1_ADDR = 0x30820000, 213 FSL_IMX7_ECSPIn_SIZE = (4 * KiB), 214 215 /* AIPS-3 End */ 216 217 /* AIPS-2 Begin */ 218 219 FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, 220 FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), 221 222 FSL_IMX7_PERFMON2_ADDR = 0x307D0000, 223 FSL_IMX7_PERFMON1_ADDR = 0x307C0000, 224 FSL_IMX7_PERFMONn_SIZE = (64 * KiB), 225 226 FSL_IMX7_DDRC_ADDR = 0x307A0000, 227 FSL_IMX7_DDRC_SIZE = (4 * KiB), 228 229 FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, 230 FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), 231 232 FSL_IMX7_TZASC_ADDR = 0x30780000, 233 FSL_IMX7_TZASC_SIZE = (64 * KiB), 234 235 FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, 236 FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), 237 238 FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, 239 FSL_IMX7_MIPI_CSI_SIZE = 0x4000, 240 241 FSL_IMX7_LCDIF_ADDR = 0x30730000, 242 FSL_IMX7_LCDIF_SIZE = 0x8000, 243 244 FSL_IMX7_CSI_ADDR = 0x30710000, 245 FSL_IMX7_CSI_SIZE = (4 * KiB), 246 247 FSL_IMX7_PXP_ADDR = 0x30700000, 248 FSL_IMX7_PXP_SIZE = 0x4000, 249 250 FSL_IMX7_EPDC_ADDR = 0x306F0000, 251 FSL_IMX7_EPDC_SIZE = (4 * KiB), 252 253 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, 254 FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), 255 256 FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, 257 FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, 258 FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, 259 260 FSL_IMX7_PWM4_ADDR = 0x30690000, 261 FSL_IMX7_PWM3_ADDR = 0x30680000, 262 FSL_IMX7_PWM2_ADDR = 0x30670000, 263 FSL_IMX7_PWM1_ADDR = 0x30660000, 264 FSL_IMX7_PWMn_SIZE = (4 * KiB), 265 266 FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, 267 FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, 268 FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), 269 270 FSL_IMX7_ECSPI4_ADDR = 0x30630000, 271 272 FSL_IMX7_ADC2_ADDR = 0x30620000, 273 FSL_IMX7_ADC1_ADDR = 0x30610000, 274 FSL_IMX7_ADCn_SIZE = (4 * KiB), 275 276 FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, 277 FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), 278 279 /* AIPS-2 End */ 280 281 /* AIPS-1 Begin */ 282 283 FSL_IMX7_CSU_ADDR = 0x303E0000, 284 FSL_IMX7_CSU_SIZE = (64 * KiB), 285 286 FSL_IMX7_RDC_ADDR = 0x303D0000, 287 FSL_IMX7_RDC_SIZE = (4 * KiB), 288 289 FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, 290 FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, 291 FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), 292 293 FSL_IMX7_GPC_ADDR = 0x303A0000, 294 295 FSL_IMX7_SRC_ADDR = 0x30390000, 296 297 FSL_IMX7_CCM_ADDR = 0x30380000, 298 299 FSL_IMX7_SNVS_HP_ADDR = 0x30370000, 300 301 FSL_IMX7_ANALOG_ADDR = 0x30360000, 302 303 FSL_IMX7_OCOTP_ADDR = 0x30350000, 304 FSL_IMX7_OCOTP_SIZE = 0x10000, 305 306 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, 307 FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), 308 309 FSL_IMX7_IOMUXC_ADDR = 0x30330000, 310 FSL_IMX7_IOMUXC_SIZE = (4 * KiB), 311 312 FSL_IMX7_KPP_ADDR = 0x30320000, 313 FSL_IMX7_KPP_SIZE = (4 * KiB), 314 315 FSL_IMX7_ROMCP_ADDR = 0x30310000, 316 FSL_IMX7_ROMCP_SIZE = (4 * KiB), 317 318 FSL_IMX7_GPT4_ADDR = 0x30300000, 319 FSL_IMX7_GPT3_ADDR = 0x302F0000, 320 FSL_IMX7_GPT2_ADDR = 0x302E0000, 321 FSL_IMX7_GPT1_ADDR = 0x302D0000, 322 323 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, 324 FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), 325 326 FSL_IMX7_WDOG4_ADDR = 0x302B0000, 327 FSL_IMX7_WDOG3_ADDR = 0x302A0000, 328 FSL_IMX7_WDOG2_ADDR = 0x30290000, 329 FSL_IMX7_WDOG1_ADDR = 0x30280000, 330 331 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, 332 333 FSL_IMX7_GPIO7_ADDR = 0x30260000, 334 FSL_IMX7_GPIO6_ADDR = 0x30250000, 335 FSL_IMX7_GPIO5_ADDR = 0x30240000, 336 FSL_IMX7_GPIO4_ADDR = 0x30230000, 337 FSL_IMX7_GPIO3_ADDR = 0x30220000, 338 FSL_IMX7_GPIO2_ADDR = 0x30210000, 339 FSL_IMX7_GPIO1_ADDR = 0x30200000, 340 341 FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, 342 FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), 343 344 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, 345 FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), 346 347 /* AIPS-1 End */ 348 349 FSL_IMX7_EIM_CS0_ADDR = 0x28000000, 350 FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), 351 352 FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, 353 FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), 354 355 FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, 356 FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), 357 358 FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, 359 FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), 360 361 FSL_IMX7_TCMU_ADDR = 0x00800000, 362 FSL_IMX7_TCMU_SIZE = (32 * KiB), 363 364 FSL_IMX7_TCML_ADDR = 0x007F8000, 365 FSL_IMX7_TCML_SIZE = (32 * KiB), 366 367 FSL_IMX7_OCRAM_S_ADDR = 0x00180000, 368 FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), 369 370 FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, 371 FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), 372 373 FSL_IMX7_ROM_ADDR = 0x00000000, 374 FSL_IMX7_ROM_SIZE = (96 * KiB), 375 }; 376 377 enum FslIMX7IRQs { 378 FSL_IMX7_USDHC1_IRQ = 22, 379 FSL_IMX7_USDHC2_IRQ = 23, 380 FSL_IMX7_USDHC3_IRQ = 24, 381 382 FSL_IMX7_UART1_IRQ = 26, 383 FSL_IMX7_UART2_IRQ = 27, 384 FSL_IMX7_UART3_IRQ = 28, 385 FSL_IMX7_UART4_IRQ = 29, 386 FSL_IMX7_UART5_IRQ = 30, 387 FSL_IMX7_UART6_IRQ = 16, 388 389 FSL_IMX7_ECSPI1_IRQ = 31, 390 FSL_IMX7_ECSPI2_IRQ = 32, 391 FSL_IMX7_ECSPI3_IRQ = 33, 392 FSL_IMX7_ECSPI4_IRQ = 34, 393 394 FSL_IMX7_I2C1_IRQ = 35, 395 FSL_IMX7_I2C2_IRQ = 36, 396 FSL_IMX7_I2C3_IRQ = 37, 397 FSL_IMX7_I2C4_IRQ = 38, 398 399 FSL_IMX7_USB1_IRQ = 43, 400 FSL_IMX7_USB2_IRQ = 42, 401 FSL_IMX7_USB3_IRQ = 40, 402 403 FSL_IMX7_GPT1_IRQ = 55, 404 FSL_IMX7_GPT2_IRQ = 54, 405 FSL_IMX7_GPT3_IRQ = 53, 406 FSL_IMX7_GPT4_IRQ = 52, 407 408 FSL_IMX7_GPIO1_LOW_IRQ = 64, 409 FSL_IMX7_GPIO1_HIGH_IRQ = 65, 410 FSL_IMX7_GPIO2_LOW_IRQ = 66, 411 FSL_IMX7_GPIO2_HIGH_IRQ = 67, 412 FSL_IMX7_GPIO3_LOW_IRQ = 68, 413 FSL_IMX7_GPIO3_HIGH_IRQ = 69, 414 FSL_IMX7_GPIO4_LOW_IRQ = 70, 415 FSL_IMX7_GPIO4_HIGH_IRQ = 71, 416 FSL_IMX7_GPIO5_LOW_IRQ = 72, 417 FSL_IMX7_GPIO5_HIGH_IRQ = 73, 418 FSL_IMX7_GPIO6_LOW_IRQ = 74, 419 FSL_IMX7_GPIO6_HIGH_IRQ = 75, 420 FSL_IMX7_GPIO7_LOW_IRQ = 76, 421 FSL_IMX7_GPIO7_HIGH_IRQ = 77, 422 423 FSL_IMX7_WDOG1_IRQ = 78, 424 FSL_IMX7_WDOG2_IRQ = 79, 425 FSL_IMX7_WDOG3_IRQ = 10, 426 FSL_IMX7_WDOG4_IRQ = 109, 427 428 FSL_IMX7_PCI_INTA_IRQ = 125, 429 FSL_IMX7_PCI_INTB_IRQ = 124, 430 FSL_IMX7_PCI_INTC_IRQ = 123, 431 FSL_IMX7_PCI_INTD_IRQ = 122, 432 433 FSL_IMX7_UART7_IRQ = 126, 434 435 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) 436 437 FSL_IMX7_MAX_IRQ = 128, 438 }; 439 440 #endif /* FSL_IMX7_H */ 441